参数资料
型号: MAX5089ATE+
厂商: Maxim Integrated Products
文件页数: 8/24页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 16TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 20 V
输入电压: 4.5 V ~ 23 V
PWM 型: 电压模式
频率 - 开关: 312kHz ~ 2.1MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-WQFN 裸露焊盘
包装: 管件
供应商设备封装: 16-TQFN-EP(5x5)
2.2MHz, 2A Buck Converters with an
Integrated High-Side Switch
Pin Description
PIN
1, 2
3
4
5
6
7
8
9
10
11
12
13
NAME
DRAIN
COMP
FB
OSC
BYPASS
V+
V L
CKO
DL
SGND
PGND
SOURCE
SYNC
FUNCTION
Internal Power MOSFET Drain Connection. Use the MOSFET as a high-side switch and connect DRAIN to the
input supply.
Transconductance Error Amplifier Output. Connect a compensation network from COMP to SGND or from
COMP to FB to SGND (see the Compensation section).
Feedback Input. Connect a resistive divider from the output to FB to SGND to set the output voltage.
Switching Frequency Set Input. Connect a resistor R OSC from OSC to SGND to set the switching frequency.
When using external synchronization, program R OSC so that (0.2 x f SYNC ) ≤ f SW ≤ ( 1.2 x f SYNC ). R OSC is still
required when external synchronization is used.
Reference Bypass Connection. Bypass to SGND with a 0.22μF or greater ceramic capacitor.
Input Supply Voltage. V+ can range from 5.5V to 23V. Connect V+ and V L together for 4.5V to 5.5V input
operation. Bypass V+ to SGND with a minimum of 0.1μF ceramic capacitor.
Internal Regulator Output. Bypass V L to SGND with a 4.7μF ceramic capacitor and to PGND with a 0.1μF
ceramic capacitor. Connect V+ to V L for 4.5V to 5.5V operation.
Clock Output (MAX5088 Only). CKO is an output with the same frequency as the converter’s switching
frequency and 115° out-of-phase. CKO is used to synchronize the MAX5088 to other MAX5088/MAX5089s.
Low-Side Synchronous Rectifier Driver (MAX5089 Only). DL sources 0.7A and sinks 1A to quickly turn on and
off the external synchronous rectifier MOSFET.
Signal Ground
Power Ground. Connect the rectifier diode’s anode, the input capacitor negative terminal, the output capacitor
negative terminal, and V L bypass capacitor negative terminal to PGND.
Internal Power MOSFET Source Connection. Connect SOURCE to the switched side of the inductor as shown in
Figure 5.
External Synchronization Input. Connect SYNC to an external logic-level clock to synchronize the MAX5088/
MAX5089. Connect SYNC to SGND when not used.
Open-Drain Active-Low Reset Output (MAX5088 Only). RESET remains low while the converter’s output is
14
RESET
PGOOD
below 92.5% of V OUT ’s nominal set point. When V OUT rises above 92.5% of its nominal set point, RESET goes
high after the reset timeout period of 200ms (typ).
Open-Drain Power-Good Output (MAX5089 Only). PGOOD remains low while the output is below 92.5% of its
nominal set point.
15
16
BST/VDD
EN
EP
Internal MOSFET Driver Supply Input. Connect BST/VDD to an external ceramic capacitor and diode (see
Figure 5).
Enable Input. A logic-low turns off the converter. A logic-high turns on the device. Connect EN to V L for an
always-on application.
Exposed Pad. Connect to SGND. Solder EP to SGND to enhance thermal dissipation.
8
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