参数资料
型号: MAX5098AATJ+T
厂商: Maxim Integrated Products
文件页数: 22/28页
文件大小: 0K
描述: IC REG BUCK BST ADJ 1A/2A 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 0.85 V,4.5 V ~ 28 V
输入电压: 4.5 V ~ 19 V
PWM 型: 电压模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 1A,2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 32-TQFN-EP(5x5)
Dual, 2.2MHz, Automotive Buck or Boost
Converter with 80V Load-Dump Protection
bandwidth and phase margin. Use a simple pole-zero
pair (Type II) compensation if the output capacitor ESR
zero frequency is below the unity-gain crossover fre-
quency (f C ). Type III compensation is necessary when
R 1
V OUT
the ESR zero frequency is higher than f C or when com-
pensating for a continuous mode boost converter that
has a right-half-plane zero.
FB_
-
g M
COMP_
Use procedure 1 to calculate the compensation net-
work components when f ZERO,ESR < f C .
Buck Converter Compensation
R 2
V REF
+
R F
C F
C CF
Procedure 1 (See Figure 4)
1) Calculate the f ZERO,ESR and LC double-pole fre-
quencies:
f ZERO , ESR =
1
2 π × ESR × C OUT
Figure 4. Type II Compensation Network
f LC =
1
2 π L OUT × C OUT
4) Place a zero at or below the LC double pole:
2) Select the unity-gain crossover frequency:
C F =
1
2 π × R F × f LC
f C ≤ SW
f
20
5) Place a high-frequency pole at f P = 0.5 x f SW .
If the f ZERO,ESR is lower than f C and close to f LC , use a
Type II compensation network where R F C F provides a
midband zero f MID,ZERO , and R F C CF provides a high-
C CF =
C F
( 2 π × 0 . 5 f SW × R F × C F ) ? 1
frequency pole.
3) Calculate modulator gain G M at the crossover fre-
quency.
Procedure 2 (See Figure 5)
If the output capacitor used is a low-ESR ceramic type,
the ESR frequency is usually far away from the targeted
unity crossover frequency (f C ). In this case, Type III
×
G M =
V IN
V OSC
×
ESR + ( 2 π × f C × L OUT ) V OUT
ESR 0 . 8
compensation is recommended. Type III compensation
provides two-pole zero pairs. The locations of the zero
and poles should be such that the phase margin peaks
f C ≤ SW
where V OSC is a peak-to-peak ramp amplitude equal to
1V.
The transconductance error amplifier gain is:
G E/A = g M x R F
The total loop gain at f C should be equal to 1:
G M x G E/A = 1
or
around f C . It is also important to place the two zeros at
or below the double pole to avoid the conditional stabil-
ity issue.
1) Select a crossover frequency:
f
20
2) Calculate the LC double-pole frequency, f LC :
R F =
V OSC ( ESR + 2 π × f C × L OUT ) × V OUT
0 . 8 × V IN × g M × ESR
f LC =
1
2 π × L OUT × C OUT
22
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