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参数资料
| 型号： | MAX5109EEE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/17页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT DUAL NV 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 设置时间： | 6µs |
| 位数： | 8 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电压，单极 |
| 采样率（每秒）： | * |
DAC Data
The 8-bit DAC data is decoded as offset binary, MSB
first, with 1 LSB = (VREFH_- VREFL_) / 256, and convert-
ed into the corresponding analog voltage as shown in
Table 9.
Applications Information
DAC Linearity and Offset Voltage
The output buffer can have a negative input offset volt-
age that would normally drive the output negative, but
with no negative supply, the output remains at GND
(Figure 9). Determine linearity using the end-point
method, measuring between code 10 (0A hex) and
code 240 (F0 hex) after calibrating the offset and gain
error (Figure 9).
External Voltage Reference
The MAX5109 features two reference inputs for each
DAC (REFH_ and REFL_). REFH_ sets the full-scale volt-
age, while REFL_ sets the zero code output. A 460k
typical input impedance is independent of the code.
Power Sequencing
The voltage applied to REFH_ and REFL_ should not
exceed VDD at any time. If proper power sequencing is
not possible, connect an external Schottky diode
between REFH_, REFL_, and VDD to ensure compliance
with the absolute maximum ratings. Do not apply signals
to the digital inputs before the device is fully powered.
Power-Supply Bypassing and
Ground Management
Digital or AC transient signals on GND can create noise
at the analog output. Return GND to the highest-quality
ground available. Bypass VDD, REFH_, and REFL_ to
GND with a 0.1F capacitor, located as close to the
device as possible. Careful PC board ground layout
minimizes crosstalk between the DAC outputs and digi-
tal inputs.
MAX5109
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial
Interface
______________________________________________________________________________________
15
DAC
CODE
OUTPUT
VOLTAGE (V)
1111 1111
1000 0000
0000 0001
0000 0000
VREFL_
Table 9. Unipolar Code Output Voltage
O
DAC CODE
NEGATIVE
OFFSET
OUTPUT
VOLTAGE
Figure 9. Effect of Negative Offset (Single Supply)
255
256
×
+
()
__
_
VV
V
REFH
REFL
128
256
×
+
(
__
_
VV
V
REFH
REFL
256
+
()
__
_
VV
V
REFH
REFL
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