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参数资料
| 型号： | MAX5214GUA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | DAC 14BIT SGL BUFFERED LP 8-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 3,000 |
| 设置时间： | 14µs |
| 位数： | 14 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 387mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-uMAX |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
3
Maxim Integrated
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface
MAX5214/MAX5216
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are
at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resistive Load (Note 6)
RL
5
kI
Short-Circuit Current
VDD = 5.5V
-25
Q
6
+25
mA
Power-Up Time
From power-down mode
25
F
s
DIGITAL INPUTS (SCLK, DIN, CS, CLR)
Input High Voltage
VIH
0.7 x
VDD
V
Input Low Voltage
VIL
0.3 x
VDD
V
Input Leakage Current
IIN
VIN = 0V or VDD
Q
0.1
Q
1
F
A
Input Capacitance
CIN
10
pF
Hysteresis Voltage
VHYS
0.15
V
DYNAMIC PERFORMANCE (Note 7)
Voltage-Output Slew Rate
SR
Positive and negative
0.5
V/Fs
Voltage-Output Settling Time
1/4 scale to 3/4 scale, to P 0.5 LSB, 14-bit
18
F
s
Reference -3dB Bandwidth
BW
Hex code = 2000 (MAX5214),
Hex code = 8000 (MAX5216)
100
kHz
Digital Feedthrough
Code = 0, all digital inputs from 0V to VDD,
SCLK < 50MHz
0.5
nVs
DAC Glitch Impulse
Major code transition
2
nVs
Output Noise
1kHz
73
nV/√Hz
10kHz
70
Integrated Output Noise
0.1Hz to 10Hz
3.5
F
VP-P
POWER REQUIREMENTS
Supply Voltage
VDD
2.7
5.5
V
Supply Current
IDD
No load; all digital inputs at 0V or VDD,
supply current only; excludes reference
input current, midscale
70
80
F
A
Power-Down Supply Current
PDIDD
No load, all digital inputs at 0V or VDD
0.4
2
F
A
TIMING CHARACTERISTICS (Notes 7 and 8) (Figures 1 and 2)
Serial Clock Frequency
fSCLK
0
50
MHz
SCLK Pulse-Width High
tCH
8
ns
SCLK Pulse-Width Low
tCL
8
ns
CS Fall to SCLK Fall Setup Time
tCSS0
8
ns
CS Fall to SCLK Fall Hold Time
tCSH0
0
ns
CS Rise to SCLK Fall Hold Time
tCSH1
0
ns
CS Rise to SCLK Fall
tCSA
12
ns
SCLK Fall to CS Fall
tCSF
100
ns
DIN to SCLK Fall Setup Time
tDS
5
ns
DIN to SCLK Fall Hold Time
tDH
4.5
ns
CS Pulse-Width High
tCSPW
20
ns
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