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参数资料
| 型号： | MAX5214GUA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/17页 |
| 文件大小： | 0K |
| 描述： | DAC 14BIT SGL BUFFERED LP 8-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 3,000 |
| 设置时间： | 14µs |
| 位数： | 14 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 387mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-uMAX |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
14
Maxim Integrated
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface
MAX5214/MAX5216
Writing to the Devices
1) Drive CS low, enabling the shift register.
2) Clock 16/24 bits of data into DIN (MSB first and LSB
last), observing the specified setup and hold times.
3) After clocking in the last data bit, drive CS high. CS
must remain high for 20ns before the next transmis-
sion is started.
Figure 1 shows a write operation for the transmission of
16 bits. If CS is driven high at any point prior to receiving
16 bits, the transmission is discarded.
Figure 2 shows a write operation for the transmission of
24 bits. If CS is driven high at any point prior to receiving
24 bits, the transmission is discarded.
Clear (CLR)
The MAX5214/MAX5216 feature an asynchronous active-
low CLR logic input that sets the DAC output to zero.
Driving CLR low clears the contents of both the input and
DAC registers and also aborts the on-going SPI com-
mand. To allow a new SPI command, drive CLR high.
Power-Down Mode
The MAX5214/MAX5216 feature a software-controlled
power-down mode. In power-down, the output discon-
nects from the buffer and is grounded with one of the
three selectable internal resistors. See Table 3 for the
selectable internal resistor values in power-down mode.
The selected mode takes effect on the 16th SCLK falling
edge of the MAX5214 and 24th SCLK falling edge of the
MAX5216. The serial interface remains active in power-
down mode. In order to abort the power-down mode
selection, pull CS high prior to the 16th (MAX5214) or
24th (MAX5216) SCLK falling edge. The contents of the
DAC register remain valid while in power-down mode,
allowing for the DAC to return to previous code by writing
0x8000 for the MAX5214 or 0x800000 for the MAX5216
(Table 3). A write to the write-through register causes the
device to immediately exit power-down mode and transi-
tion to the requested code (see Tables 1 and 2).
Table 3. Power-Down Modes
Table 4. MAX5216 Input Code vs. Output Voltage
Table 5. MAX5214 Input Code vs. Output Voltage
A1
A0
DESCRIPTION
DAC OPERATION
CONDITION
0
DAC powers up and returns to its previous code setting.
Normal operation
0
1
DAC powers down; OUT is high impedance.
Power-down
1
0
DAC powers down; OUT connects to ground through an internal 100kI resistor.
1
DAC powers down; OUT connects to ground through an internal 1kI resistor.
DAC LATCH CONTENTS
ANALOG OUTPUT (VOUT)
MSB g LSB
1111 1111 1111 11XX
VREF x (16,383/16,383)
1000 0000 0000 00XX
VREF x (8,192/16,383) = 1/2 VREF
0000 0000 0000 01XX
VREF x (1/16,383)
0000 0000 0000 00XX
0V
DAC LATCH CONTENTS
ANALOG OUTPUT (VOUT)
MSB g LSB
1111 1111 1111 1111
VREF x (65,535/65,535)
1000 0000 0000 0000
VREF x (32,768/65,535) = 1/2 VREF
0000 0000 0000 0001
VREF x (1/65,535)
0000 0000 0000 0000
0V
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