参数资料
型号: MAX5312EAE
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: DAC
英文描述: +-10V, 12-Bit, Serial, Voltage-Output DAC
中文描述: SERIAL INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PDSO16
封装: 5.30 MM, MO-150, SSOP-16
文件页数: 13/19页
文件大小: 1086K
代理商: MAX5312EAE
Detailed Description
The MAX5312 12-bit DAC operates from either single or
dual supplies. Dual ±12V to ±15V power supplies pro-
vide a bipolar ±5V to ±10V output, or a unipolar 0 to 10V
output. Single 12V to 15V power supplies provide only a
unipolar 0 to 10V output. The reference input accepts
voltages from 2V to 5.25V. The DAC features INL and
DNL less than ±1 LSB (max), a fast 10μs settling time,
and a hardware-shutdown mode that reduces current
consumption to 3.5μA (max). The device features a
10MHz SPI-/QSPI-/MICROWIRE-compatible serial inter-
face that operates with 3V or 5V logic, an asynchronous
load input, and a serial-data output. The device offers a
CLR
that sets the DAC output to 0V. Figure 1 shows the
functional diagram of the MAX5312.
Serial Interface
An SPI-/QSPI-/MICROWIRE-compatible serial interface
allows complete control of the DAC through a 16-bit
control word. The first 4 bits form the control bits that
determine register loading and software-shutdown
functions. The last 12 bits form the DAC data. The 16-
bit word is entered MSB first.
Table 1 shows the serial-data format. Table 2 shows
the interface commands.
The MAX5312 can be programmed while in shutdown.
The serial interface contains three registers: a 16-bit shift
register, a 12-bit input register, and a 12-bit DAC register
(Figure 1). The shift register accepts data from the serial
interface. The input register acts as a holding register for
data going to the DAC register and isolates the shift reg-
ister from the DAC register. The DAC register controls
the DAC ladder and thus the output voltage. Any update
in the DAC register updates the output voltage.
M
±10V, 12-Bit, Serial, Voltage-Output DAC
______________________________________________________________________________________
13
V
SS
V
CC
OUT
DOUT
DGND
SGND
V
DD
DIN
SCLK
REF
AGND
SERIAL INTERFACE
AND CONTROL
2R
2R
2R
2R
INPUT REGISTER
DAC REGISTER
12-BIT DAC
A1
A2
SW1
SW2
SW3
16-BIT SHIFT REGISTER
12
12
12
LDAC
CLR
CS
UNI/BIP
SHDN
MAX5312
Figure 1. Functional Diagram
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