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参数资料
| 型号： | MAX5312EAE |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | DAC |
| 英文描述： | +-10V, 12-Bit, Serial, Voltage-Output DAC |
| 中文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封装： | 5.30 MM, MO-150, SSOP-16 |
| 文件页数： | 6/19页 |
| 文件大小： | 1086K |
| 代理商： | MAX5312EAE |
M
±10V, 12-Bit, Serial, Voltage-Output DAC
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DD
= +15V, V
SS
= -15V or 0V, V
CC
= +2.7V to +5.5V, AGND = DGND = SGND = 0, V
REF
= 5V, R
LOAD
= 2k
, C
LOAD
= 250pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
SCLK Frequency
SCLK Clock Period
t
CP
SCLK Pulse-Width High
t
CH
For nondaisy-chain use
SCLK Pulse-Width Low
t
CL
For nondaisy-chain use
CS
Fall to SCLK Rise Setup Time
t
CSS
+2.7V
≤
V
CC
≤
+3.6V
SCLK Rise to
CS
Rise Hold Time
t
CSH
+4.5V
≤
V
CC
≤
+5.5V
DIN Setup Time
t
DS
DIN Hold Time
t
DH
LDAC
Pulse Width
t
LD
+2.7V
≤
V
CC
≤
+3.6V
CS
Rise to
LDAC
Low Setup Time
t
LDS
+4.5V
≤
V
CC
≤
+5.5V
C
LOAD
= 20pF, +2.7V
≤
V
CC
≤
+3.6V
SCLK Fall to DOUT Valid
Propagation Delay
C
LOAD
= 20pF, +4.5V
≤
V
CC
≤
+5.5V
SCLK Rise to
CS
Fall Delay
t
CS0
CS
Low to DOUT Valid Time
t
CSE
C
LOAD
= 20pF
CS
High to DOUT Disabled Time
t
CSD
CS
Rise to SCLK Rise Hold Time
t
CS1
+2.7V
≤
V
CC
≤
+3.6V
CS
Pulse-Width High
t
CSW
+4.5V
≤
V
CC
≤
+5.5V
CLR
Pulse-Width Low
t
CLR
MIN
TYP
MAX
10
UNITS
MHz
ns
ns
ns
ns
100
45
45
40
15
10
20
10
50
ns
ns
ns
ns
100
50
ns
100
80
t
DO1
ns
10
ns
ns
ns
ns
120
120
50
200
100
ns
50
ns
Note 1:
Output unloaded, digital inputs = V
CC
or DGND.
Note 2:
V
DD
= +14.5V to +15.5V,
V
SS
= -15.5V to -14.5V, code = FFF.
Note 3:
Measured from code 14hex to FFFhex.
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