参数资料
型号: MAX5316GTG+T
厂商: Maxim Integrated Products
文件页数: 16/33页
文件大小: 0K
描述: IC DAC 16BIT SPI 24TQFN
产品培训模块: Obsolescence Mitigation Program
标准包装: 2,500
设置时间: 3µs
位数: 16
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 模拟和数字,双 ±
功率耗散(最大): 2.29W
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x5)
包装: 带卷 (TR)
输出数目和类型: 1 电压,单极;1 电压,双极
23
MAX5316
16-Bit, ±1 LSB Accuracy Voltage Output
DAC with SPI Interface
Serial Interface
Overview
The SPI interface supports speeds up to 50MHz. When
CS is high, the remaining interface inputs are disabled to
reduce transient currents. The interface supports daisy
chaining to enable multiple device to be controlled on
the same SPI bus.
The device has a double-buffered interface consisting of
two register banks: the input register and the DAC reg-
ister. The input register for DIN is connected directly to
the 24-bit SPI input shift register. The DAC latch contains
the DAC code and is loaded as defined in the LDAC and
A valid SPI frame is 24-bit wide with 4-bit command R3
to R0, 16-bit data D15 to D0, and 4 unused LSBs. A full
24-bit SPI command sequence is required for all SPI
command operations, regardless of the number of data
bits actually used for the command. Any commands
terminating with less than a full 24-bit sequence will be
aborted without impacting the operation of the part (sub-
ject to tCSA timing requirements). Data is not written into
the SPI input register or DAC and it continues to hold the
preceding valid data. If a command sequence with more
than 24 bits is provided, the command will be executed
on the 24th SCLK falling edge and the remainder of the
command will be ignored.
All SPI commands result in the device assuming con-
trol of the DOUT line from the first SCLK edge through
the 24th SCLK edge. After relinquishing the DOUT line,
the MAX5316 will return to a high-impedance state. An
optional bus hold circuit can be engaged to hold DOUT
at its last bit value while not interfering with other devices
on the bus.
DOUT is disabled at power-up and must be enabled
through the SPI interface. When enabled, DOUT echoes
the 4-bit command plus 16-bit data, which is being
programmed. During readback, DOUT echoes the 4-bit
command followed by the true readback data depending
upon the type of read command. Table 4 shows the bit
positions for DOUT and DIN within the 24-bit SPI frame.
The device is designed such that SCLK idles low, and
DIN and DOUT change on the rising clock edge and get
latched on the falling clock edge. The SPI host controller
should be set accordingly.
Figure 4. BUSY and LDAC Timing
DIN
SCLK
BUSY
LDAC
VOUT
OPTION 1
INPUT REGISTER LOADED
OPTION 2
OPTION 3
OPTION 4
(USED AS INPUT)
X1
2X
21
22
23
X
tBUSY
tS
tCBF
tLDH
50ns
tLDPW
BUSY PULLED LOW EXTERNALLY
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