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参数资料
| 型号： | MAX532ACPE+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC MDAC 12BIT DUAL SER 16-DIP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 25 |
| 设置时间： | 2.5µs |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 842mW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 16-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 16-PDIP |
| 包装： | 管件 |
| 输出数目和类型： | 2 电压，单极；2 电压，双极 |
| 采样率（每秒）： | * |
| 产品目录页面： | 1425 (CN2011-ZH PDF) |
MAX532
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2k, CL = 100pF,
VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYMBOL
VREF = 100mVp-p sine wave;
DAC latch loaded with all 1s
1.0
MHz
VREF = 20Vp-p 10kHz sine wave;
DAC latch loaded with all 0s
-77
dB
Full-Power Bandwidth
125
kHz
THD
Total Harmonic Distortion
-90
dB
Output Noise Voltage
0.1Hz to 10Hz
2
VRMS
Digital Crosstalk
DACA code all 1s, DACB code transition from all 0s to all 1s
10
nV-s
Digital Feedthrough
CS = 1; transitions on SCLK, LDAC, DIN
1.1
nV-s
PARAMETER
tCL
CONDITIONS
MIN
TYP
MAX
SCLK Pulse Width Low
UNITS
SYMBOL
fCLK
tCH
80
ns
tDS
50
ns
tCSS1
CS Rise to SCLK Rise Setup Time
SCLK Clock Frequency
50
ns
tCSS0
CS Fall to SCLK Rise Setup Time
6.25
MHz
50
ns
tDH
DIN to SCLK Rise Hold Time
0
ns
SCLK Pulse Width High
80
ns
Multiplying Feedthrough
Error
Unity-Gain Small-Signal
Bandwidth
VREF = 20Vp-p sine wave;
DAC latch loaded with all 1s
VREF = 6VRMS, 1kHz sine wave;
DAC latch loaded with all 1s
Note 1: Static performance tested at VDD = +15V, VSS = -15V. Performance over supplies guaranteed by PSR test.
Note 2: Guaranteed by design. Not subject to production testing.
Note 3: Open-drain output.
TIMING CHARACTERISTICS
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5)
tCSH0
SCLK Fall to
CS Fall Hold Time
5
ns
tCSH1
SCLK Rise to
CS Rise Hold Time
80
ns
tCSW
CS Pulse Width High
120
ns
tDO
SCLK Fall to DOUT Valid (Note 6)
CL = 20pF, RPULL-UP = 1k to 5V
0
200
ns
tDV
CS Fall to DOUT Enable (Note 7)
CL = 20pF, RPULL-UP = 1k to 5V
100
ns
tTR
CS Rise to DOUT Disable (Note 7)
CL = 20pF, RPULL-UP = 1k to 5V
60
ns
tLDAC
LDAC Pulse Width Low
60
ns
tLDACS
CS Rise to LDAC Fall Setup Time
100
ns
DIN to SCLK Rise Setup Time
Note 4: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0V to 5V.
Note 5: See Figure 1.
Note 6: Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any
larger passive RC pull-up delay.
Note 7: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX532ACPE+ | 功能描述:数模转换器- DAC 12-Bit 2Ch Precision DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX532ACWE | 功能描述:数模转换器- DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX532ACWE+ | 功能描述:数模转换器- DAC 12-Bit 2Ch Precision DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX532ACWE+T | 功能描述:数模转换器- DAC 12-Bit 2Ch Precision DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX532ACWE-T | 功能描述:数模转换器- DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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