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参数资料
型号： MAX5525ETC+T
厂商： Maxim Integrated Products
文件页数： 19/23页
文件大小： 0K
描述： IC DAC 10BIT DUAL ULP 12-TQFN
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 2,500
设置时间： 660µs
位数： 10
数据接口： MICROWIRE?，QSPI?，串行，SPI?
转换器数目： 2
电压电源： 单电源
功率耗散（最大）： 1.35W
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 12-WQFN 裸露焊盘
供应商设备封装： 12-TQFN-EP（4x4）
包装： 带卷 (TR)
输出数目和类型： 2 电压，单极；2 电压，双极
采样率（每秒）： *
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
_______________________________________________________________________________________
5
Note 1: Linearity is tested within codes 24 to 1020.
Note 2: Offset is tested at code 24.
Note 3: Gain is tested at code 1023. For the MAX5524/MAX5525, FB_ is connected to its respective OUT_.
Note 4: Guaranteed by design. Not production testsed
Note 5: VDD must be a minimum of 1.8V.
Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded.
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN.
Note 9: All digital inputs at VDD or GND.
Note 10: Load = 10k
in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5522/MAX5524) or VREF = 3.9V (MAX5523/MAX5525).
TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (VDD = 4.5V to 5.5V )
Serial Clock Frequency
fSCLK
0
16.7
MHz
DIN to SCLK Rise Setup Time
tDS
15
ns
DIN to SCLK Rise Hold Time
tDH
0ns
SCLK Pulse-Width High
tCH
24
ns
SCLK Pulse-Width Low
tCL
24
ns
CS Pulse-Width High
tCSW
100
ns
SCLK Rise to
CS Rise Hold Time
tCSH
0ns
CS Fall to SCLK Rise Setup Time
tCSS
20
ns
SCLK Fall to
CS Fall Setup
tCSO
0ns
CS Rise to SCK Rise Hold Time
tCS1
20
ns
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25
°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V )
Serial Clock Frequency
fSCLK
0
10
MHz
DIN to SCLK Rise Setup Time
tDS
24
ns
DIN to SCLK Rise Hold Time
tDH
0ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
CS Pulse-Width High
tCSW
150
ns
SCLK Rise to
CS Rise Hold Time
tCSH
0ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Fall to
CS Fall Setup
tCSO
0ns
CS Rise to SCK Rise Hold Time
tCS1
30
ns
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