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参数资料
| 型号： | MAX5852ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/18页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT DUAL 165MSPS 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 设置时间： | 12ns |
| 位数： | 8 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 200M |
MAX5852
Dual, 8-Bit, 165Msps, Current-Output DAC
10
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Pin Description
PIN
NAME
FUNCTION
1
DA7/PD
Channel A Input Data Bit 7 (MSB)/Power-Down
2
DA6/DACEN Channel A Input Data Bit 6/DAC Enable Control
3
DA5/IDE
Channel A Input Data Bit 5/Interleaved Data Enable
4
DA4/REN
Channel A Input Data Bit 4/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.
5
DA3/G3
Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3
6
DA2/G2
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2
7
DA1/G1
Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1
8
DA0/G0
Channel A Input Data Bit 0 (LSB)/Channel A Gain Adjustment Bit 0
9, 10, 21,
22
N.C.
No Connection. Do not connect to these pins.
11
DB7
Channel B Input Data Bit 7 (MSB)
12
DB6
Channel B Input Data Bit 6
13
DB5
Channel B Input Data Bit 5
14
DB4
Channel B Input Data Bit 4
15
DB3
Channel B Input Data Bit 3
16
DVDD
Digital Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
17
DGND
Digital Ground
18
DB2
Channel B Input Data Bit 2
19
DB1
Channel B Input Data Bit 1
20
DB0
Channel B Input Data Bit 0 (LSB)
23
CW
Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.
24
DCE
Active-Low Differential Clock Enable Input. Drive DCE low to enable differential clock inputs
CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the single-
ended CLK input.
25
CLKXP
Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
26
CLKXN
Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXN to CVDD when the differential clock is disabled.
27, 30
CVDD
Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
28
CLK
Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a single-
ended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-ended
output that mirrors differential clock inputs CLKXP and CLKXN. See the Clock Modes section for more
information on CLK.
29
CGND
Clock Ground
31
REFO
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1F capacitor.
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| MAX5852EVKIT | 功能描述:数模转换器- DAC Evaluation Kit for the MAX5851 MAX5852 RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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