参数资料
型号: MAX5856AECM+TD
厂商: Maxim Integrated Products
文件页数: 10/23页
文件大小: 0K
描述: IC DAC 8BIT DUAL 300MSPS 48-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
设置时间: 11ns
位数: 8
数据接口: 并联
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 792mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-TQFP 裸露焊盘(7x7)
包装: 带卷 (TR)
输出数目和类型: 2 电流,单极
采样率(每秒): 300M
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
18
______________________________________________________________________________________
External Reference
To disable the internal reference of the MAX5856A, con-
nect REN to AVDD. Apply a temperature-stable, external
reference to REFO to set the full-scale output (Figure 5).
For improved accuracy and drift performance, choose a
fixed output voltage reference such as the MAX6520
bandgap reference.
Detailed Timing
The MAX5856A accepts an input data rate up to
165MHz or a DAC conversion rate of up to 300MHz.
The inputs are latched on the rising edge of the clock.
The outputs are latched on the following rising edge.
IFS
0.1F
10F
AVDD
RSET
IREF
REFR
AVDD
REFO
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE ARRAY
EXTERNAL
1.24V
REFERENCE
REN
MAX5856A
MAX6520
AGND
Figure 5. MAX5856A with External Reference
PLLEN
F2EN
F1EN
DIFFERENTIAL CLOCK
FREQUENCY
fCLKDIFF (MHz)
CLOCK
FREQUENCY
fCLK (MHz)
DAC RATE
fDAC
INTERPOLATION
MAX SIGNAL
BANDWIDTH
(MHz)
10
0
N/A (tie CLXP low
and CLXN high)
0 to 165 (input)
fCLK
1x
82
10
1
N/A (tie CLXP low
and CLXN high)
75 to 150 (input)
2* fCLK
2x
63
11
1
N/A (tie CLXP low
and CLXN high)
37 to 75 (input)
4* fCLK
4x
31
00
0
0 to 165
fCLKDIFF (output)
fCLKDIFF
1x
82
00
1
0 to 300
fCLKDIFF / 2 (output)
fCLKDIFF
2x
63
01
1
0 to 300
fCLKDIFF / 4 (output)
fCLKDIFF
4x
31
01
0
11
0
Illegal
Table 5. PLL Clocking Modes
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