参数资料
型号: MAX5858AECM+D
厂商: Maxim Integrated Products
文件页数: 5/25页
文件大小: 0K
描述: IC DAC 10BIT DUAL 300MSPS 48TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 250
设置时间: 11ns
位数: 10
数据接口: 并联
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 816mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-TQFP 裸露焊盘(7x7)
包装: 托盘
输出数目和类型: 2 电流,单极
采样率(每秒): 300M
MAX5858A
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
______________________________________________________________________________________
13
Pin Description (continued)
PIN
NAME
FUNCTION
13
DB9
Channel B Input Data Bit 9 (MSB)
14
DB8
Channel B Input Data Bit 8
15
DB7
Channel B Input Data Bit 7
16
DB6
Channel B Input Data Bit 6
17
DB5
Channel B Input Data Bit 5
20
CLK
Clock Output/Input. CLK becomes an input when the PLL is enabled. CLK is an output when the PLL
is disabled.
21
IDE
Interleave Data Mode Enable. When IDE is high, data for both DAC channels is written through port A
(bits DA9–DA0). When IDE is low, channel A data is latched on the rising edge of CLK and channel B
data is latched on the falling edge of CLK.
22
DB4
Channel B Input Data Bit 4
23
DB3
Channel B Input Data Bit 3
24
DB2
Channel B Input Data Bit 2
25
DB1
Channel B Input Data Bit 1
26
DB0
Channel B Input Data Bit 0 (LSB)
27
CW
Active-Low Control-Word Write Pulse. The control word is latched on the falling edge of CW.
28
LOCK
PLL Lock Signal Output. High level indicates that PLL is locked to the CLK signal.
29
PLLEN
PLL Enabled Input. PLL in enabled when PLLEN is high.
30
CLKXP
Differential Clock Input Positive Terminal. Connect to PGND when the PLL is enabled. Bypass CLKXP
with a 0.01F capacitor to PGND when CLKXN is in single-ended mode.
31
CLKXN
Differential Clock Input Negative Terminal. Connect to PVDD when the PLL is enabled. Bypass CLKXN
with a 0.01F capacitor to PGND when CLKXP is in single-ended mode.
32
PVDD
PLL Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section.
33
PGND
PLL Ground
34
PLLF
PLL Loop Filter. Connect a 4.12k
resistor in series with a 100pF capacitor between PLLF and
PGND.
35
REN
Active-Low Reference Enable. Connect REN to AGND to activate the on-chip 1.24V reference.
36
REFO
Reference I/O. REFO serves as the reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as the output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1F capacitor.
37, 38
N.C.
No Connection. Not connected internally.
39
REFR
Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET
between REFR and AGND. The output full-scale current is equal to 32
× VREFO/RSET.
40, 46
AVDD
Analog Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section.
41
OUTNB
Channel B Negative Analog Current Output
42
OUTPB
Channel B Positive Analog Current Output
43
AGND
Analog Ground
44
OUTNA
Channel A Negative Analog Current Output
45
OUTPA
Channel A Positive Analog Current Output
EP
Exposed Paddle. Connect to the ground plane.
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