MAX5858A
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
18
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IFS
CCOMP*
REFR
IREF
REFO
MAX4040
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE ARRAY
*COMPENSATION CAPACITOR (CCOMP
≈ 100nF).
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
REN
MAX5858A
IREF =
VREF
RSET
AGND
Figure 4. Setting IFS with the Internal 1.24V Reference and the Control Amplifier
PLL Clock Multiplier and
Clocking Modes
The MAX5858A features an on-chip PLL clock multiplier
that generates all internal, synchronized high-speed
clock signals required by the input data latches, inter-
polation filters, and DAC cores. The on-chip PLL
includes a phase-detector, VCO, prescalar, and
charge-pump circuits. The PLL can be enabled or dis-
abled through PLLEN. To enable PLL set PLLEN = 1.
With the PLL enabled (PLLEN = 1) and 4x/2x interpola-
tion enabled, an external low-frequency clock reference
source is applied to CLK pin. The clock reference
source serves as the input data clock. The on-chip PLL
multiplies the clock reference by a factor of two (2x) or
a factor of four (4x). The input data rate range and CLK
frequency are set by the selected interpolation mode.
In 2x interpolation mode, the data rate range is 75MHz
to 150MHz. In 4x interpolation mode the data rate
range is 37.5MHz to 75MHz.
Note: When the PLL is enabled, CLK becomes an
input, requiring CLKXP to be pulled low and CLKXN to
be pulled high. To obtain best phase noise perfor-
mance, disable the PLL function.
With the PLL disabled (PLLEN = 0) and 4x/2x interpola-
tion enabled, an external conversion clock is applied at
CLKXN/CLKXP. The conversion clock at CLKXN/CLKXP
has a frequency range of 0MHz to 300MHz (see Table
5). This clock is buffered and distributed by the
MAX5858A to drive the interpolation filters and DAC
cores. In this mode, CLK becomes a divide-by-N (DIV-
N) output at either a divide-by-two or divide-by-four
rate. The DIV-N factor is set by the selected interpola-
tion mode. The CLK output, at DIV-N rate, must be
used to synchronize data into the MAX5858A data
ports. In this mode, keep the capacitive load at the CLK
output low (10pF or less at fDAC = 165MHz).
With the interpolation disabled (1x mode) and the PLL
disabled (PLLEN = 0), the input clock at CLKXN/CLKXP
can be used to directly update the DAC cores. In this
mode, the maximum data rate is 165MHz.
Internal Reference and Control Amplifier
The MAX5858A provides an integrated 50ppm/°C,
1.24V, low-noise bandgap reference that can be dis-
abled and overridden with an external reference volt-
age. REFO serves either as an external reference input
or an integrated reference output. If REN is connected
to AGND, the internal reference is selected and REFO
provides a 1.24V (50A) output. Buffer REFO with an
external amplifier, when driving a heavy load.
The MAX5858A also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (IFS) for both outputs of the devices.
Calculate the output current as:
IFS = 32 IREF
where IREF is the reference output current (IREF =
VREFO/RSET) and IFS is the full-scale output current. RSET
is the reference resistor that determines the amplifier out-
put current of the MAX5858A (Figure 4). This current is
mirrored into the current-source array where IFS is equally
distributed between matched current segments and
summed to valid output current readings for the DACs.