参数资料
型号: MAX5895EGK+D
厂商: Maxim Integrated Products
文件页数: 10/31页
文件大小: 0K
描述: IC DAC 16BIT 500MSPS DUAL 68-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
设置时间: 11ns
位数: 16
数据接口: 并联
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 511mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 68-VFQFN 裸露焊盘
供应商设备封装: 68-QFN 裸露焊盘(10x10)
包装: 管件
输出数目和类型: 2 电流,单极
采样率(每秒): 500M
产品目录页面: 1398 (CN2011-ZH PDF)
MAX5895
tionship and detects if the phase drifts more than ±1
data clock cycle. If this occurs, the synchronizer auto-
matically reestablishes synchronization. However, dur-
ing the resynchronization phase, up to 8 data words
may be lost or repeated.
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.
DATACLK Modes
The MAX5895 has a main DATACLK available at
pin 14. An alternate DATACLK is available at pin 27
(DATACLK/B14) when configured in single-port data
input mode (bit 5, address 02h). The DATACLK can be
configured to accept an input clock signal for latching
the input data, or to source a clock signal that can drive
up to 10pF load while latching the input data (bit 3,
address 02h). If DATACLK is configured as an output, it
is frequency divided from the CLKP/CLKN input,
depending on the operating mode, see Table 4.
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
18
______________________________________________________________________________________
INPUT
MODE
INTERPOLATION
RATE
fDATA:fCLK
fDAC:fCLK
1x
1:1
1:2
2x
1:1
4x
1:2
1:1
Single
Port
8x
1:4
1:1
1x
1:1
2x
1:2
1:1
4x
1:4
1:1
Dual Port
8x
1:8
1:1
Table 4. Clock Frequency Ratios in
Various Modes
Figure 4. Data Input Timing Diagram
tD
tDS
tCLK
CLKP–CLKN
DATACLK
A0–A15/B0–B15
tDH
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