参数资料
型号: MAX5945CAX+T
厂商: Maxim Integrated Products
文件页数: 40/44页
文件大小: 0K
描述: IC NETWORK PWR CTRL 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
控制器类型: 网络电源控制器
接口: I²C
电源电压: 3.3V
电流 - 电源: 4.2mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 带卷 (TR)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +32V to +60V, VEE = 0V, VDD to DGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD = (DGND + 3.3V), TA = +25°C. Currents are positive when entering the pin and
negative otherwise.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal Input Pullup/Pulldown
Resistor
RDIN
Pullup (pulldown) resistor to VDD (DGND) to set
default level
25
50
75
k
Open-Drain Output Low
Voltage
VOL
ISINK = 15mA
0.4
V
Open-Drain Leakage
IOL
Open-drain high impedance, VO = 3.3V
2
A
TIMING
Startup Time
tSTART
Time during which a current limit set by VSU_LIM
is allowed, starts when the GATE_
is turned on (Note 8)
50
60
70
ms
Fault Time
tFAULT
Maximum allowed time for an overcurrent
condition set by VFLT_LIM after startup (Note 8)
50
60
70
ms
Port Turn-Off Time
tOFF
Minimum delay between any port turning off,
does not apply in the case of a reset
0.5
0.75
1.0
ms
Detection Time
tDET
Maximum time allowed before detection
is completed
320
ms
Midspan Mode Detection
Delay
tDMID
2.0
2.4
s
Classification Time
tCLASS
Time allowed for classification
40
ms
VEEUVLO Turn-On Delay
tDLY
Time VAGND must be above the VEEUVLO
thresholds before the device operates
24
ms
RSTR bits = 00
16 x
tFAULT
RSTR bits = 01
32 x
tFAULT
RSTR bits = 10
64 x
tFAULT
Restart Timer
tRESTART
Time a port has to wait
before turning on after an
overcurrent fault,
RSTR_EN bit = high
RSTR bits = 11
0
ms
Watchdog Clock Period
tWD
Rate of decrement of the watchdog timer
164
ms
TIMING CHARACTERISTICS for 2-WIRE FAST MODE (Figures 5 and 6)
Serial Clock Frequency
fSCL
(Note 9)
400
kHz
Bus Free Time Between a
STOP and a START Condition
tBUF
(Note 9)
1.2
s
Hold Time for Start Condition
tHD, STA
(Note 9)
0.6
s
Low Period of the SCL Clock
tLOW
(Note 9)
1.2
s
High Period of the SCL Clock
tHIGH
(Note 9)
0.6
s
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