参数资料
型号: MAX5949AESA+
厂商: Maxim Integrated
文件页数: 9/18页
文件大小: 186K
描述: IC HOT SWAP CONTROL 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: -20 V ~ -80 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 1423 (CN2011-ZH PDF)
Board Insertion
Figure 7a shows a typical hot-swap circuit for -48V sys-
tems. When the circuit board first makes contact with
the backplane, the DRAIN to GATE capacitance (C
gd
)
of Q1 pulls up the GATE voltage to roughly IV
EE
x C
gd
/
(C
gd
+ C
gs
)I. The MAX5949_ features an internal
dynamic clamp between GATE and V
EE
to keep the
gate-to-source voltage of Q1 low during hot insertion,
preventing Q1 from passing an uncontrolled current to
the load. For most applications, the internal dynamic
clamp between GATE and V
EE
of the MAX5949A/
MAX5949B eliminates the need for an external gate-to-
source capacitor C1. Resistor R3 limits the current into
the clamp circuitry during card insertion.
Power-Supply Ramping
The MAX5949_ can reside either on the backplane or
the removable circuit board (Figure 7a). Power is deliv-
ered to the load by placing an external n-channel
MOSFET pass transistor in the power-supply path.
After the circuit board is inserted into the backplane
and the supply voltage at V
EE
is stable and within the
undervoltage and overvoltage tolerance, the MAX5949_
turn on Q1. The MAX5949_ gradually turn on the exter-
nal MOSFET by charging the gate of Q1 with a 45礎
current source.
Capacitor C2 provides a feedback signal to accurately
limit the inrush current. The value of C
2
can be
calculated:
where C
L
is the total load capacitance, C3 + C4, and
I
PU
is the MAX5949_ gate pullup current.
Figure 7b shows the inrush current waveform. The cur-
rent through C2 controls the GATE voltage. At the end
of the DRAIN ramp, the GATE voltage is charged to its
final value. The GATE-to-SENSE clamp limits the maxi-
mum V
GS
to about 18V under any condition.
Board Removal
If the card is removed from a live backplane, the output
capacitor on the card may not be immediately dis-
charged. While the output capacitor is discharging, the
MAX5949_ continues to operate as if the input supply
were still connected because the output capacitor tem-
porarily supplies operating current to the IC. If the cir-
cuit is connected as in Figure 7a, the voltage at the UV
pin falls below the V
UVL
, and the MAX5949_ turns off
the external MOSFET. If R4 in the circuit is connected
directly to the -48V return, the external MOSFET
remains on until the capacitor is discharged sufficiently
to drop the UV pin voltage to V
UVL
.
C
I    x C
I
PU
L
INRUSH
2
=
   
-48V Hot-Swap Controllers
with External R
SENSE
_______________________________________________________________________________________   9
V
EE
SENSE
GATE
DRAIN
V
DD
OV
UV
PWRGD
MAX5949B
-48V RTN
-48V
R4
549k&
1%
R5
6.49k&
1%
R6
10k&
1%
R1
0.02&
5%
R3
1k&
5%
R2
10&
5%
C1**
470nF
25V
Q1
IRF530
C2
15nF
100V
GATE IN
VICOR
VI-J3D-CY
V
IN+
V
IN-
C4
100礔
100V
C3
0.1礔
100V
C5
100礔
10V
*
10nF
-48V RTN
(SHORT PIN)
*DIODES INC. SMAT70A.
**OPTIONAL.
Figure 7a. Inrush Control Circuitry
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