参数资料
型号: MAX5965BEAX+
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet; Package: SSOP;36 pin;163 mm² ; Temperature: -40°C to +85°C
中文描述: 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO36
封装: ROHS COMPLIANT, SSOP-36
文件页数: 10/54页
文件大小: 1525K
代理商: MAX5965BEAX+
MAX5965A/MAX5965B
High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
18
______________________________________________________________________________________
A valid PD has a 25k
discovery signature characteristic
as specified in the IEEE 802.3af/at standard. Table 1
shows the IEEE 802.3af/at specification for a PSE detect-
ing a valid PD signature. See the
Typical Operating
Circuits and Figure 1a (Detection, Classification, and
Power-Up Port Sequence). The MAX5965A/MAX5965B
can probe and categorize different types of devices con-
nected to the port such as: a valid PD, an open circuit, a
low resistive load, a high resistive load, a high capacitive
load, a positive DC supply, or a negative DC supply.
During detection, the MAX5965A/MAX5965B keep the
external MOSFET off and force two probe voltages
through the DET_ input. The current through the DET_
input is measured as well as the voltage at OUT_. A
two-point slope measurement is used as specified by
the IEEE 802.3af standard to verify the device connect-
ed to the port. The MAX5965A/MAX5965B implement
appropriate settling times and a 100ms digital integra-
tion to reject 50Hz/60Hz power-line noise coupling.
An external diode, in series with the DET_ input, restricts
PD detection to the first quadrant as specified by the
IEEE 802.3af/at standard. To prevent damage to non-PD
devices, and to protect themselves from an output short
circuit, the MAX5965A/MAX5965B limit the current into
DET_ to less than 2mA maximum during PD detection.
In midspan mode, the MAX5965A/MAX5965B wait 2.2s
before attempting another detection cycle after every
failed detection. The first detection, however, happens
immediately after issuing the detection command.
High-Capacitance Detection
The CLC_EN bit in register R23h[5] enables the large
capacitor detection feature for legacy PD devices.
When CLC_EN = 1, the high-capacitance detection limit
is extended up to 150F. CLC_EN = 0 is the default
condition for the normal capacitor size detection. See
Table 1 and the
Register Map and Description section.
Table 1. PSE PI Detection Modes Electrical Requirement
(Table 33-2 of the IEEE 802.3af Standard)
PARAMETER
SYMBOL
MIN
MAX
UNITS
ADDITIONAL INFORMATION
Open-Circuit Voltage
VOC
30
V
In detection mode only
Short-Circuit Current
ISC
5
mA
In detection mode only
Valid Test Voltage
VVALID
2.8
10
V
Voltage Difference
Between Test Points
VTEST
1—
V
Time Between Any Two
Test Points
tBP
2—
ms
This timing implies a 500Hz maximum probing
frequency
Slew Rate
VSLEW
0.1
V/s
Accept Signature
Resistance
RGOOD
19
26.5
k
Reject Signature
Resistance
RBAD
< 15
> 33
k
Open-Circuit Resistance
ROPEN
500
k
Accept Signature
Capacitance
CGOOD
150
nF
Reject Signature
Capacitance
CBAD
10
F
Signature Offset Voltage
Tolerance
VOS
0
2.0
V
Signature Offset Current
Tolerance
IOS
012
A
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