参数资料
型号: MAX6369KA-T
厂商: Maxim Integrated Products
文件页数: 5/10页
文件大小: 0K
描述: IC WATCHDOG TIMER SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 监视器电路
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 可调节/可选择
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 剪切带 (CT)
其它名称: MAX6369KA-TCT
MAX6369–MAX6374
Pin-Selectable Watchdog Timers
Pin Description
PIN
1
2
3
4
5
6
7
8
NAME
WDI
GND
N.C.
SET0
SET1
SET2
WDO
V CC
FUNCTION
Watchdog Input. If WDI remains either high or low for the duration of the watchdog timeout period (t WD ), WDO
triggers a pulse. The internal watchdog timer clears whenever a WDO is asserted or whenever WDI sees a
rising or falling edge.
Ground
Not Connected. Do not make any connection to this pin.
Set Zero. Logic input for selecting startup delay and watchdog timeout periods. See Table 1 for timing details.
Set One. Logic input for selecting startup delay and watchdog timeout periods. See Table 1 for timing details.
Set Two. Logic input for selecting startup delay and watchdog timeout periods. See Table 1 for timing details.
Watchdog Output. Pulses low for the watchdog output pulse width, t WDO , when the internal watchdog times
out. The MAX6369/MAX6371/MAX6373 have open-drain outputs and require a pull-up resistor. The
MAX6370/MAX6372/MAX6374 outputs are push-pull.
Supply Voltage (+2.5V to +5.5V)
Table 1. Minimum Timeout Settings
LOGIC INPUTS
MAX6369/MAX6370
MAX6371/MAX6372
MAX6373/MAX6374
SET2
0
0
0
0
1
1
1
1
SET1
0
0
1
1
0
0
1
1
SET0
0
1
0
1
0
1
0
1
t DELAY , t WD
1ms
10ms
30ms
Disabled
100ms
1s
10s
60s
t DELAY = 60s, t WD
1ms
3ms
10ms
Disabled
100ms
300ms
3s
60s
t DELAY
3ms
3s
60s
Disabled
200 μ s
First Edge
First Edge
60s
t WD
3ms
3s
1s
Disabled
30 μ s
1s
10s
10s
Detailed Description
The MAX6369–MAX6374 are flexible watchdog circuits
for monitoring μP activity. During normal operation, the
internal timer is cleared each time the μP toggles the
WDI with a valid logic transition (low to high or high to
low) within the selected timeout period (t WD ). The WDO
remains high as long as the input is strobed within the
selected timeout period. If the input is not strobed
before the timeout period expires, the watchdog output
is asserted low for the watchdog output pulse width
(t WDO ). The device type and the state of the three logic
control pins (SET0, SET1, and SET2) determine watch-
dog timing characteristics. The three basic timing varia-
tions for the watchdog startup delay and the normal
Maxim Integrated
watchdog timeout period are summarized below (see
Table 1 for the timeout characteristics for all devices in
the family):
? Watchdog Startup Delay:
Provides an initial delay before the watchdog timer is
started.
Allows time for the μP system to power up and initial-
ize before assuming responsibility for normal watch-
dog timer updates.
Includes several fixed or pin-selectable startup delay
options from 200μs to 60s, and an option to wait for
the first watchdog input transition before starting the
watchdog timer.
5
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