参数资料
型号: MAX6446UK23L+T
厂商: Maxim Integrated Products
文件页数: 8/13页
文件大小: 0K
描述: IC MPU RESET 2.313V SOT23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.313V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 标准包装
其它名称: MAX6446UK23L+TDKR
μP Reset Circuits with Long Manual Reset
Setup Period
+3.3V
+1.5V
CORE SUPPLY I/O SUPPLY
5V
3.3V
V CC
RESET
RESET
V CC
MAX6451
RSTIN
MR1
μ P
DIGITAL INPUT
MAX6444
MAX6446
MAX6448
100k ?
μ P
MAX6450
MAX6452
GND
MR2
RESET
RESET
N
SMART CARD DETECT:
IMMEDIATE ONE-SHOT
WHEN MANUAL
RESET CLOSES
FRONT-PANEL SWITCH
STANDARD μ P INPUT
AND t MR MANUAL
RESET DELAY
GND
Figure 7. MAX6451/MAX6452 Application Circuit
a microprocessor for general-purpose I/O control. MR2
monitors a switch to detect when a smart card is inserted.
When the switch is closed high (card inserted), RESET
one-shot pulses low for 140ms. MR2 is internally
debounced for 210ms to prevent false resets when the
smart card is removed.
Interfacing to Other Voltages
for Logic Compatibility
The open-drain RESET output can be used to interface
to a μP with other logic levels. As shown in Figure 8, the
open-drain output can be connected to voltages from 0
to 6V.
Generally, the pullup resistor connected to the RESET
connects to the supply voltage that is being monitored
at the IC’s V CC pin. However, some systems may use
the open-drain output to level-shift from the monitored
supply to reset circuitry powered by some other supply
(Figure 8). Keep in mind that as the supervisor’s V CC
decreases toward 1V, so does the IC’s ability to sink
current at RESET . RESET is pulled high as V CC decays
toward 0. The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
connected.
Figure 8. Interfacing to Other Voltage Levels
Ensuring a Valid RESET Down to
V CC = 0V (Push-Pull RESET )
When V CC falls below 1V, RESET current-sinking capa-
bilities decline drastically. The high-impedance CMOS-
logic inputs connected to RESET can drift to
undetermined voltages. This presents no problems in
most applications, because most μPs and other circuitry
do not operate with V CC below 1V.
In applications in which RESET must be valid down to
0V, add a pulldown resistor between RESET and GND
for the push-pull outputs. The resistor sinks any stray
leakage currents, holding RESET low (Figure 9). The
value of the pulldown resistor is not critical; 100k ? is
large enough not to load RESET and small enough to
pull RESET to ground. The external pulldown cannot be
used with the open-drain reset outputs.
Transient Immunity
In addition to issuing a reset to the μP during power-up,
power-down, and brownout conditions, these supervi-
sors are relatively immune to short-duration falling tran-
sients (glitches). The graph Maximum Transient Duration
vs. Reset Threshold Overdrive in the Typical Operating
Characteristics section shows this relationship.
8
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