参数资料
型号: MAX6639YAEE+T
厂商: Maxim Integrated
文件页数: 3/22页
文件大小: 0K
描述: IC TEMP MONITOR 2CH 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 风扇控制,温度监控器
传感器类型: 内部和外部
感应温度: 0°C ~ 150°C,外部传感器
拓扑: ADC,PWM 发生器,转速计计数器
输出类型: I²C?/SMBus?
输出警报:
输出风扇:
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
MAX6639/MAX6639F
2-Channel Temperature Monitor with Dual,
Automatic, PWM Fan-Speed Controller
ELECTRICAL CHARACTERISTICS (continued)
(V CC = +3.0V to +3.6V, T A = 0 ° C to +125 ° C, unless otherwise noted. Typical values are at V CC = +3.3V, T A = +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS AND OUTPUTS
Output Low Voltage (Sink
Current) ( OT , ALERT , FANFAIL ,
THERM , SDA, PWM1, and PWM2)
V OL
ALERT , FANFAIL , THERM , OT , SDA
I SINK = 6mA
PWM1, PWM2, I SINK = 4mA
0.4
0.4
V
Output High Leakage Current
( OT , ALERT , FANFAIL , THERM ,
I OH
1
μA
SDA, PWM1, and PWM2)
Logic-Low Input Voltage (SDA,
SCL, THERM , TACH1, TACH2)
V IL
0.8
V
Logic-High Input Voltage (SDA,
SCL, THERM , TACH1, TACH2)
V IH
V CC = 3.3V
2.1
V
Input Leakage Current (SDA,
SCL, THERM , TACH1, TACH2)
Input Capacitance
C IN
V IN = V CC or GND
5
1
μA
pF
SMBus TIMING (Note 2)
Serial Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time Between STOP
and START Conditions
SMBus START Condition Setup
Time
START Condition Hold Time
STOP Condition Setup Time
Data Setup Time
Data Hold Time
SMBus Fall Time
SMBus Rise Time
f SCL
t LOW
t HIGH
t BUF
t SU:STA
t HD:STO
t SU:STO
t SU:DAT
t HD:DAT
t F
t R
(Note 3)
10% to 10%
90% to 90%
90% of SMBCLK to 90% of SMBDATA
10% of SDA to 10% of SCL
90% of SCL to 10% of SDA
10% of SDA to 10% of SCL
10% of SCL to 10% of SDA (Note 4)
10
4
4.7
4.7
4.7
4
4
250
300
100
300
1000
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
SMBus Timeout
t TIMEOUT
58
74
90
ms
Note 1:
Note 2:
Note 3:
Note 4:
All parameters tested at a single temperature. Specifications are guaranteed by design.
Timing specifications guaranteed by design.
The serial interface resets when SCL is low for more than t TIMEOUT .
A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of SCL's falling edge.
Maxim Integrated
3
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