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| 型号： | MAX6705SKA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU LV SOT23-8 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 推挽式，图腾柱 |
| 复位： | 低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 2.93V，可调 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 |
| 供应商设备封装： | SOT-23-8 |
| 包装： | 标准包装 |
| 其它名称： | MAX6705SKA+TDKR |
Low-Voltage, SOT23 μP Supervisors with Power-
Fail In/Out, Manual Reset, and Watchdog Timer
ELECTRICAL CHARACTERISTICS (continued)
(V CC = +4.25V to +5.5V for L/M versions, V CC = +2.55V to +3.6V for the T/S/R versions, V CC = +2.1V to +2.75V for the Z/Y versions.
T A = -40 ° C to +125 ° C, unless otherwise specified. Typical values are at T A = +25 ° C.) (Note 1)
PARAMETER
PFI, RST_IN1, RST_IN2
Leakage Current
SYMBOL
(Note 2)
CONDITIONS
T A = -40 ° C to +85 ° C
T A = -40 ° C to +125 ° C
MIN
-50
-200
TYP
MAX
+50
+200
UNITS
nA
PFI to PFO Delay
t PF
1
μs
MR Input Voltage
MR Minimum Input Pulse
MR Glitch Rejection
MR to Reset Delay
V CC Rising to WDO Delay
V IL
V IH
t MD
MAX6701(A)/MAX6702(A)/MAX6703(A)/
MAX6705(A)/MAX6706(A)/MAX6707(A)
0.7 x V CC
1
100
200
100
0.3 x V CC
V
μs
ns
ns
ns
MR Pullup Resistance
25
50
75
k ?
Watchdog Timeout Period
WDI Pulse Width
WDI Input Voltage
WDI Input Current
RESET , WDO Output Low
(Push-Pull or Open Drain)
t WD
t WDI
V IL
V IH
I WDI
V OL
T A = -40 ° C to +85 ° C
T A = -40 ° C to +125 ° C
(Note 2)
WDI = 0V or V CC
V CC ≥ 1.0V, I SINK = 50μA, output asserted
(T A = 0 ° C to +125 ° C)
V CC ≥ 1.2V, I SINK = 100μA, output asserted
V CC ≥ 2.55V, I SINK = 1.2mA, output asserted
1.12
0.96
50
0.7 x V CC
-1
1.6
2.4
2.52
0.3 x V CC
+1
0.3
0.3
0.3
s
ns
V
μA
V
V CC ≥ 4.25V, I SINK = 3.2mA, output asserted
0.4
PFO Output Low
(Push-Pull or Open Drain)
RESET , WDO , PFO Output
High (Push-Pull Only)
V OL
V OH
V CC ≥ 1.80V, I SINK = 200μA, output asserted
V CC ≥ 2.55V, I SINK = 1.2mA, output asserted
V CC ≥ 4.25V, I SINK = 3.2mA, output asserted
V CC ≥ 2.7V, I SOURCE = 500μA, output not asserted
V CC ≥ 4.75V, I SOURCE = 800μA, output not asserted
0.8 x V CC
0.8 x V CC
0.3
0.3
0.4
V
V
RESET , WDO , PFO Output
Open-Drain Leakage
I LKG
V CC > V TH , output not asserted
1.0
μA
Current
RESET Output High
(Push-Pull Only)
V OH
V CC ≥ 1.0V, I SOURCE = 1μA, reset asserted
(T A = 0 ° C to +125 ° C)
V CC ≥ 1.2V, I SOURCE = 50μA, reset asserted
V CC ≥ 2.55V, I SOURCE = 500μA, reset asserted
0.8 x V CC
0.8 x V CC
0.8 x V CC
V
V CC ≥ 4.25V, I SOURCE = 800μA, reset asserted
0.8 x V CC
RESET Output Low
(Push-Pull Only)
V OL
V CC ≥ 2.7V, I SINK = 1.2mA, reset not asserted
V CC ≥ 4.75V, I SINK = 3.2mA, reset not asserted
0.3
0.4
V
Note 1: Over-temperature limits are guaranteed by design and not production tested. Devices are tested at T A = +25 ° C.
Note 2: Guaranteed by design. Not production tested.
_______________________________________________________________________________________
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