参数资料
型号: MAX6750KA29+T
厂商: Maxim Integrated Products
文件页数: 5/14页
文件大小: 0K
描述: IC MPU/RESET CIRC SOT23-8
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 多压监控器
监视电压数目: 2
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 可调节/可选择
电压 - 阀值: 2.925V,可调
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 标准包装
产品目录页面: 1418 (CN2011-ZH PDF)
其它名称: MAX6750KA29+TDKR
MAX6746–MAX6753r
μP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Typical Operating Characteristics (continued)
(V CC = +5V, T A = +25°C, unless otherwise noted.)
V CC TO RESET DELAY
vs. TEMPERATURE (V CC FALLING)
RESET AND WATCHDOG
TIMEOUT PERIOD vs. SUPPLY VOLTAGE
RESET AND WATCHING TIMEOUT
PERIOD vs. SUPPLY VOLTAGE
27.0
V CC FALLING AT 1mV/μs
0.60
C SWT = C SRT = 100pF
9.0
C SWT = C SRT = 1500p        F
26.6
26.2
25.8
25.4
25.0
0.56
0.52
0.48
0.44
0.40
8.5
8.0
7.5
7.0
6.5
6.0
RESET
WATCHDOG
-50
-25
0
25
50
75
100
125
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TEMPERATURE ( ° C)
V CC (V)
V CC (V)
Pin Description
PIN
MAX6746
MAX6747
1
MAX6748–
MAX6751
MAX6752
MAX6753
NAME
MR
FUNCTION
Manual Reset Input. Pull MR low to manually reset the device. Reset
remains asserted for the reset timeout period after MR is released.
Reset Input. High-impedance input to the adjustable reset comparator.
1
RESET IN
Connect RESET IN to the center point of an external resistor-divider to
set the threshold of the externally monitored voltage.
1
SET0
Logic Input. SET0 selects watchdog window ratio or disables the
watchdog timer. See Table 1.
Watchdog Timeout Input.
MAX6746–MAX6751: Connect a capacitor between SWT and ground to
set the basic watchdog timeout period (t WD ). Determine the period by
the formula t WD = 5.06 x 10 6 x C SWT with t WD in seconds and C SWT in
Farads. Extend the basic watchdog timeout period by using the WDS
input. Connect SWT to ground to disable the watchdog timer function.
2
2
2
SWT
MAX6752/MAX6753: Connect a capacitor between SWT and ground to
set the slow watchdog timeout period (t WD2 ). Determine the slow
watchdog period by the formula: t WD2 = 0.65 x 10 9 x C SWT with t WD2 in
seconds and C SWT in Farads. The fast watchdog timeout period is set
by pinstrapping SET0 and SET1 (Connect SET0 high and SET1 low to
disable the watchdog timer function.) See Table 1.
Reset Timeout Input. Connect a capacitor from SRT to GND to select
3
3
3
SRT
the reset timeout period. Determine the period as follows: t RP = 5.06 x
10 6 x C SRT with t RP in seconds and C SRT in Farads.
4
4
4
GND
Ground
Maxim Integrated
5
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