参数资料
型号: MAX6823MUK+T
厂商: Maxim Integrated Products
文件页数: 5/9页
文件大小: 0K
描述: IC MPU SUPERVISOR SOT23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.38V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 带卷 (TR)
Low-Voltage SOT23 μP Supervisors with
Manual Reset and Watchdog Timer
Pin Description
PIN NUMBERS
MAX6821 MAX6822 MAX6823 MAX6824 MAX6825
PIN
NAME
FUNCTION
Active-Low Open-Drain or Push-Pull Reset Output. RESET
changes from high to low when the V CC input drops below the
1
1
1
1
RESET
selected reset threshold, MR is pulled low, or the watchdog
triggers a reset. RESET remains low for the reset timeout period
after V CC exceeds the device reset threshold, MR goes low to
high, or the watchdog triggers a reset.
Active-High Push-Pull Reset Output. RESET changes from low to
high when the V CC input drops below the selected reset threshold,
1
3
3
RESET
MR is pulled low, or the watchdog triggers a reset. RESET remains
high for the reset timeout period after V CC exceeds the device
reset threshold, MR goes low to high, or the watchdog triggers a
reset.
2
2
2
2
2
GND
Ground
Active-Low Manual Reset Input. Internal 50k ? pullup to V CC . Pull
3
3
3
4
MR
low to force a reset. Reset remains active as long as MR is low
and for the reset timeout period after MR goes high. Leave
unconnected or connect to V CC if unused.
Watchdog Input. If WDI remains high or low for longer than the
watchdog timeout period, the internal watchdog timer runs out and
a reset is triggered for the reset timeout period. The internal
4
4
4
4
WDI
watchdog timer clears whenever reset is asserted, the manual
reset is asserted, or WDI sees a rising or falling edge. If WDI is
left unconnected or is connected to a three-stated buffer output,
the watchdog feature is disabled.
5
5
5
5
5
V CC
Supply Voltage and Input for Reset Threshold Monitor
Detailed Description
RESET /RESET Output
A μP ’ s reset input starts the μP in a known state. The
MAX6821 – MAX6825 μP supervisory circuits assert a
reset to prevent code-execution errors during power-
up, power-down, and brownout conditions. Whenever
V CC falls below the reset threshold, the reset output
asserts low for RESET and high for RESET. Once V CC
exceeds the reset threshold, an internal timer keeps the
reset output asserted for the specified reset timeout
period (t RP ); after this interval, reset output returns to its
original state (see Figure 2).
Manual Reset Input
Many μP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. On the MAX6821/
MAX6822/MAX6823/MAX6825, a logic low on MR
asserts a reset. Reset remains asserted while MR is
low, and for the timeout period (140ms min) after it
returns high. MR has an internal 50k ? pullup resistor,
so it can be left open if not used. This input can be dri-
ven with CMOS logic levels or with open-drain/collector
outputs. Connect a normally open momentary switch
from MR to GND to create a manual reset function;
external debounce circuitry is not required. If MR is dri-
ven from long cables or the device is used in a noisy
environment, connect a 0.1μF capacitor from MR to
GND to provide additional noise immunity.
Watchdog Input
In the MAX6821 – MAX6824, the watchdog circuit moni-
tors the μP ’ s activity. If the μP does not toggle (low to
high or high to low) the watchdog input (WDI) within the
watchdog timeout period (1.6s nominal), reset asserts
for the reset timoeout period. The internal 1.6s timer
can be cleared by either a reset pulse or by toggling
WDI. The WDI can detect pulses as short as 50ns.
While reset is asserted, the timer remains cleared and
does not count. As soon as reset is released, the timer
starts counting (see Figure 3).
_______________________________________________________________________________________
5
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