参数资料
型号: MAX6823MUK+T
厂商: Maxim Integrated Products
文件页数: 7/9页
文件大小: 0K
描述: IC MPU SUPERVISOR SOT23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.38V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 带卷 (TR)
Low-Voltage SOT23 μP Supervisors with
Manual Reset and Watchdog Timer
V CC
t RST
V CC
V CC
RESET*
t RP
t WD
t RP
MAX6822
RESET
RESET
RESET
μ P
WDI
GENERATOR
*RESET IS THE INVERSE OF RESET.
GND
GND
Figure 3. Watchdog Timing Relationship
Figure 4. Interfacing Open-Drain RESET to μPs with
Bidirectional Reset I/O
Resets are issued to the μP during power-up, power-
down, and brownout conditions. The Typical Operating
Characteristics show a graph of the MAX6821 –
MAX6825 ’ s Maximum V CC Transient Duration vs. Reset
Threshold Overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going V CC pulses, starting at the standard monitored
voltage and ending below the reset threshold by the
magnitude indicated (reset threshold overdrive). The
graph shows the maximum pulse width that a negative-
going V CC transient can typically have without trigger-
ing a reset pulse. As the amplitude of the transient
increases (i.e., goes farther below the reset threshold),
the maximum allowable pulse width decreases.
Typically, a V CC transient that goes 100mV below the
reset threshold and lasts for 20μs or less will not trigger
a reset pulse.
Watchdog Software Considerations
One way to help the watchdog timer monitor software
execution more closely is to set and reset the watch-
dog input at different points in the program, rather than
pulsing the watchdog input high-low-high or low-high-
low. This technique avoids a stuck loop, in which the
watchdog timer would continue to be reset inside the
loop, keeping the watchdog from timing out.
Figure 5 shows an example of a flow diagram where
the I/O driving the watchdog input is set high at the
beginning of the program, set low at the beginning of
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
RETURN
Figure 5. Watchdog Flow Diagram
Typical Operating Circuit
V CC
V CC
V CC
every subroutine or loop, then set high again when the
program returns to the beginning. If the program
should hang in any subroutine, the problem would
quickly be corrected, since the I/O is continually set
RESET
MAX6823
RESET
μ P
low and the watchdog timer is allowed to time out,
causing a reset or interrupt to be issued. As described
MANUAL
MR
GND
WDI
I/O
in the Watchdog Input Current section, this scheme
results in higher time average WDI input current than
does leaving WDI low for the majority of the timeout
period and periodically pulsing it low-high-low.
RESET
_______________________________________________________________________________________
7
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