参数资料
型号: MAX6850AEE-T
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 显示驱动器
英文描述: 4-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
中文描述: VACUUM FLUOR DISPLAY DRIVER, PDSO16
封装: 0.150 INCH, 0.25 MM PITCH, MO-137, QSOP-16
文件页数: 15/34页
文件大小: 485K
代理商: MAX6850AEE-T
MAX6850
put latches. In the default condition, VFBLANK is low to
enable its VFD tube driver outputs to follow the state of
the VFD tube driver’s output latches. The VFBLANK out-
put is used for PWM intensity control and to disable the
VFD tube driver in shutdown.
Multiplex Architecture
The multiplex engine transmits grid and anode control
data to the external VFD driver using VFCLK, VFDOUT,
and VFLOAD. The number of data bits m transmitted is
set by the user in the shift-limit register (Table 30). Figure
12 is the VFD multiplex timing diagram.
The essential rules for multiplex action are as follows:
The external VFD driver’s data latch contains the
data for the current grid being displayed.
The VFBLANK input is controlled to provide the
PWM intensity control.
The VFCLK and VFDOUT outputs are used to fill the
external VFD driver’s shift register with the multiplex
data for the next grid, during the multiplex timeslot
for the current grid.
The VFLOAD output loads the new grid-anode data
pattern at the start of its multiplex cycle.
4-Wire Interfaced, 7-, 14-, and 16-Segment Alpha-
numeric Vacuum-Fluorescent Display Controller
22
______________________________________________________________________________________
REGISTER DATA
GRIDS
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
HEX CODE
Display has 1 grid: G0 (always)
0x03
0
0x00
Display has 2 grids: G0 and G1
0x03
0
1
0x01
Display has 3 grids: G0 to G2
0x03
0
1
0
0x02
Display has 4 grids: G0 to G3
0x03
0
1
0x03
UP TO
0x03
0
——
Display has 45 grids: G0 to G44
0x03
0
1
0
1
0
0x2C
Display has 46 grids: G0 to G45
0x03
0
1
0
1
0
1
0x2D
Display has 47 grids: G0 to G46
0x03
0
1
0
1
0
0x2E
Display has 48 grids: G0 to G47
0x03
0
1
0
1
0x2F
Table 26. Grids Register Format
VFCLK
VFDOUT
VFLOAD
DD0
DD1 DD2
DD3
DD4 DD5
DD6 DD7
DD8 DD9 DD10
M-4
M-3
M-2
M-1
M
(M IS VALUE IN SHIFT-LIMIT REGISTER)
GRID 1's DATA, SENT DURING GRID 0's TIMESLOT
GRID 0's 100
s MULTIPLEX TIMESLOT
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
START OF NEXT
CYCLE
1.25
s
1.25
s
1
s1s
100
s TIMESLOT
GRID 0
100
s TIMESLOT
GRID 1
100
s TIMESLOT
GRID N-4
100
s TIMESLOT
GRID N-3
100
s TIMESLOT
GRID N-2
100
s TIMESLOT
GRID N-1
100
s TIMESLOT
GRID 0
Figure 12. VFD Multiplex Timing Diagram
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