参数资料
型号: MAX6876ETX+T
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: EEPROM-Programmable, Quad, Power-Supply Tracker/Sequencer Circuit
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC36
封装: 6 X 6 MM, 0.80 MM HEIGHT, MO-220WJJD-1, TQFN-36
文件页数: 15/39页
文件大小: 425K
代理商: MAX6876ETX+T
MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
22
______________________________________________________________________________________
Outputs
GATE_
The MAX6876 features four GATE_ outputs to drive four
external n-channel FET gates. The following conditions
must be met before GATE_ begins enhancing the
external n-channel FET_:
1) All monitored inputs (IN1–IN4) are above their
selected thresholds (0.5V to 5.5V)
2) At least one IN_ input or VCC is above 2.7V
3) Drive ENABLE high
4) TRKEN > 1.25V
At power-up mode, GATE_ voltages are enhanced con-
trol loops so all OUT_ voltages track together at a user-
selected slew rate. Each GATE_ is internally pulled up
to 5V above its relative IN_ voltage to fully enhance the
external n-channel FET when power-up is complete. In
sequencing/tracking mode, a gate delay timeout is
internally counted prior to the start of each control ramp
(see Figures 1 and 2 and Table 9).
FAULT
The MAX6876 offers an open-drain, active-low tracking
fault alarm (FAULT). FAULT asserts low when a power-
up phase is not completed within the specified fault
period or if tracking voltages fail by more than ±250mV.
For multiple MAX6876 applications, FAULT is an
input/output pin and communicates fault information
between master/slave devices. Connect all FAULT pins
in an ORed configuration to force simultaneous shut-
down on all MAX6876s (Table 10.) See the Typical
Application Circuit.
Power-Good Outputs (PG_)
The MAX6876 features four power-good (PG_) outputs.
PG_ outputs are open-drain and require external
pullups.
When the OUT_ output is within the selected percent-
age of the IN_ voltage range (VTH_PG), the correspond-
ing PG_ output goes high impedance. PG_ stays low
until the OUT_ voltage exceeds the programmable
VTH_PG threshold for more than tPOK (Table 11).
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
“000” gate-delay timer value = 25s
“001” gate-delay timer value = 12.5ms
“010” gate-delay timer value = 25.0ms
“011” gate-delay timer value = 50.0ms
“100” gate-delay timer value = 100.0ms
“101” gate-delay timer value = 200.0ms
“110” gate-delay timer value = 400.0ms
0Fh
2Fh
[7:5]
“111” gate-delay timer value = 1600.0ms
Table 9. GATE-Delay Time Settings
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
[7:6]
Bit [7:6] “00” fault power-up timer value = 25ms
“01” fault power-up timer value = 50ms
“10” fault power-up timer value = 100ms
“11” fault power-up timer value = 200ms
0Ah
2Ah
[5:4]
Bit [5:4] “00” fault power-down timer value = 25ms
“01” fault power-down timer value = 50ms
“10” fault power-down timer value = 100ms
“11” fault power-down timer value = 200ms
Table 10. FAULT Power-Up and Power-Down Time Settings
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