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MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
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17
Registers
Tables 1 and 2 show the register map, as well as the
register descriptions for the MAX6917.
Control Register
The control register contains bits for configuring the
MAX6917 for custom applications. Bit D0 (BATT ON
BLINK) and D1 (BATT LO BLINK) are used to enable a
1Hz blink rate on BATT_ON and BATT_LO when they
are active; see the Battery Test section for details. D2
(WD TIME) and D3 (WD EN) are used to enable the
watchdog function and select its timeout. For details,
see the Watchdog Input section. D5 (INT/EXT TEST)
sets whether the internal resistor ratio or an external
resistor ratio is to be used to check for the low-battery
condition; see the Battery Test section for details. D6
(XTAL EN) enables the crystal-fail-detect circuitry when
set. See the Crystal-Fail Detect section for details. D7
(WP) is the write protect bit. Before any write operation
to the registers (except the control register) or RAM, bit
7 must be zero. When set to one, the write-protect bit
prevents write operations to any register (except the
control register) or RAM location.
Timekeeping and Alarm Thresholds Registers
Time and date data is stored in the timekeeping and
alarm threshold registers in BCD format as shown in Table
1. The weekday data in the day register is user defined (a
common format is 1 = Sunday, 2 = Monday, etc.)
AM/PM and 12hr/24hr Mode
For both timekeeping and alarm threshold registers
(Table 1), D7 of the hours register is defined as the
12hr or 24hr mode-select bit. When set to one, the 12hr
mode is selected. In the 12hr mode, D5 is the AM/PM
bit with logic one being PM. In the 24hr mode, D5 is the
second 10hr bit (20hr to 23hr).
Clock-Burst Mode
Addressing the clock-burst register specifies burst-
mode operation. In this mode, the first eight clock/cal-
endar registers (seven timekeeping and the control
register) can be consecutively read or written to by
using the address/command byte 00h for a write or 01h
for a read (Table 1). If the write-protect bit is set to one
when a write-clock/calendar-burst mode is specified,
no data transfer occurs to any of the seven timekeeping
registers or the control register. When writing to the
clock/calendar registers in the burst mode, the first
eight registers must be written to for the data to be
transferred.
RAM
The static RAM consists of 96 x 8 bits addressed con-
secutively in the RAM address/command space. Even
address/commands (3Eh to FCh) are used for RAM
writes and odd address/commands (3Fh to FDh) are
used for RAM reads (Table 2).
RAM-Burst Mode
Sending the RAM-burst address/command (FEh for
write, FFh for read) specifies burst-mode operation. In
this mode, the 96 RAM locations can be consecutively
read or written to starting with bit 7 of address/com-
mand 3Eh for writes, and 3Fh for reads. A burst read
outputs all 96 bytes of RAM. When writing to RAM in
burst mode, it is not necessary to write all 96 bytes for
the data to transfer; each complete byte written is
transferred to the RAM. When reading from RAM, data
are output until all 96 bytes have been read, or until the
data transfer is stopped by the I2C master.
Status Register
The status register contains individual bits for monitor-
ing the status of several functions of the MAX6917. Bits
D0–D3 are unused and always read zero (Table 1). D4
(ALM OUT) reflects the state of the alarm function; see
the Alarm-Generation Function section for details. D5
(BATT LO) indicates the state of the battery connected
to VBATT; see the Battery Test section for more informa-
tion. D6 (DATA VALID) alerts the user if all power was
lost. See the Data Valid Bit section for details. D7 (XTAL
FAIL) is the output of the crystal-fail detect circuit. See
the Crystal-Fail Detect section for details.