参数资料
型号: MAX6952EAX+
厂商: Maxim Integrated
文件页数: 13/21页
文件大小: 0K
描述: IC DRVR DSPL LED 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 30
显示器类型: LED
配置: 5 x 7(矩阵)
接口: 4 线串行
数字或字符: 4 位数字
电流 - 电源: 12mA
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 管件
4-Wire Interfaced, 2.7V to 5.5V,
4-Digit 5 ? 7 Matrix LED Display Driver
Table 14. Character Map
MSB
Table 18 shows an example of data (characters 0, 1,
and 2) being stored in the first three user-defined font
locations, illustrating the orientation of the data bits.
LSB
x000
x001
x010
x011
x100
x101
x110
x111
Table 19 shows the six sequential write commands
required to set a MAX6953's font character RAM02 with
0000
RAM00
RAM16
the data to display character 2 given in the font RAM
illustration above.
0001
RAM01
RAM17
Multiplex Clock and Blink Timing
The OSC pin can be fitted with capacitor C SET to GND
(to use the internal RC multiplex oscillator), or driven by
0010
RAM02
RAM18
an external clock. The multiplex clock frequency deter-
mines the multiplex scan rate and the blink timing. The
display scan rate is calculated by dividing the frequency
0011
RAM03
RAM19
at OSC by 5600. With OSC at 4 MHz, each display digit
is enabled for 100μs and the display scan rate is
714.29Hz.
0100
RAM04
RAM20
The on-chip oscillator may be accurate enough for
applications using a single device. If an exact blink rate
is required, use an external clock ranging between
0101
RAM05
RAM21
1MHz and 8MHz to drive OSC. The OSC inputs of multi-
ple MAX6952s can be tied together to a common exter-
nal clock to make the devices blink at the same rate.
0110
RAM06
RAM22
The relative blink phasing of multiple MAX6952s can be
synchronized by setting the T bit in the control register
for all the devices in quick succession (Table 11).
0111
RAM07
RAM23
If the serial interfaces of multiple MAX6952s are daisy-
chained by connecting DOUT of one device to DIN of
the next, then synchronization is achieved automatically
1000
1001
1010
1011
1100
1101
1110
1111
RAM08
RAM09
RAM10
RAM11
RAM12
RAM13
RAM14
RAM15
by updating the control register for all devices together.
For MAX6952s, the devices can be synchronized by
transmitting the serial data for the control register, and
then toggling the CS pin for each device, either togeth-
er or in quick succession. Figure 7 is the multiplex tim-
ing diagram.
Blink Output
The blink output indicates the blink phase, and is high
during the P0 period and low during the P1 period.
Blink phase status can also be read back as the P bit in
the configuration register (Table 13). Typical uses for
this output are:
? To provide an interrupt to the processor so that seg-
ment data can be changed synchronous to the
blinking. For example, a clock application may have
colon segments blinking every second between
hours and minute digits, and the minute display is
best changed in step with the colon segments. Also,
if the rising edge of blink is detected, there is half a
blink period to change the P1 digit data. Similarly, if
the falling edge of blink is detected, the user has
half a blink period to change the P0 digit data.
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