参数资料
型号: MAX6953EAX+T
厂商: Maxim Integrated
文件页数: 13/23页
文件大小: 0K
描述: IC DRVR DSPL LED 36-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
显示器类型: LED
配置: 5 x 7(矩阵)
接口: I²C
数字或字符: 4 位数字
电流 - 电源: 12mA
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
供应商设备封装: 36-SSOP
包装: 带卷 (TR)
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 ? 7
Matrix LED Display Driver
Table 10. Global Blink Enable/Disable (E Data Bit D3) Format
MODE
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Blink function is disabled.
Blink function is enabled.
P
P
X
X
R
R
T
T
0
1
B
B
X
X
S
S
Table 11. Digit Register Mapping with
Blink Globally Enabled
Global Blink Enable/Disable (E Data Bit D3) Format
The E bit globally enables or disables the blink feature
of the device (Table 10). When blink is globally
SEGMENT’S
BIT SETTING
IN PLANE P1
0
0
1
1
SEGMENT’S
BIT SETTING
IN PLANE P0
0
1
0
1
SEGMENT
BEHAVIOR
Segment off
Segment on only
during the 1st half of
each blink period
Segment on only
during the 2nd half of
each blink period
Segment on
enabled, then the digit data in both planes P0 and P1
are used to control the display (Table 11).
When blink is globally disabled, then only the digit data
in plane P0 is used to control the display. The digit data
in plane P1 is ignored.
Global Blink Timing Synchronization (T Data Bit D4)
Format
By setting the T bit in multiple MAX6953s at the same
time (or in quick succession), the blink timing can be
synchronized across all the devices (Table 12). Note
that the display multiplexing sequence is also reset,
which might give rise to a one-time display flicker when
the register is written.
Table 12. Global Blink Timing Synchronization (T Data Bit D4) Format
MODE
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Blink timing counters are unaffected.
Blink timing counters are reset during the I 2 C
acknowledge.
P
P
X
X
R
R
0
1
E
E
B
B
X
X
S
S
Table 13. Global Clear Digit Data (R Data Bit D5) Format
MODE
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Digit data for both planes P0 and P1 are unaffected.
Digit data for both planes P0 and P1 are cleared during
I 2 C acknowledge.
P
P
X
X
0
1
T
T
E
E
B
B
X
X
S
S
Table 14. Blink Phase Readback (P Data Bit D7) Format
MODE
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
P1 blink phase
P0 blink phase
0
1
X
X
R
R
T
T
E
E
B
B
X
X
S
S
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