参数资料
型号: MAX6955ATL+T
厂商: Maxim Integrated
文件页数: 16/43页
文件大小: 0K
描述: IC DRVR DSPL LED 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: LED
配置: 7、14、16 段
接口: I²C
电流 - 电源: 22mA
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
MAX6955
2-Wire Interfaced, 2.7V to 5.5V LED Display
Driver with I/O Expander and Key Scan
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
D15
D14
D13
D12
D11
D10
D9
D8
ACKNOWLEDGE FROM MAX6955
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
P
Figure 7. Command Byte Received
R/W
ACKNOWLEDGE FROM MAX6955
ACKNOWLEDGE FROM MAX6955
ACKNOWLEDGE FROM MAX6955
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6955's REGISTERS
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX6955
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
A
P
R/W
1 BYTE
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 8. Command and Single Data Byte Received
ACKNOWLEDGE FROM MAX6955
ACKNOWLEDGE FROM MAX6955
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6955's REGISTERS
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX6955
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
A
P
R/W
n BYTE
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 9. n Data Bytes Received
Each key press is scanned twice in a 25.6ms time peri-
od with a nominal oscillator frequency of 4MHz, as
shown in Figure 12. In the first key test period of 1.6ms,
input level at ports P0–P3 (Key_A, Key_B, Key_C, and
Key_D) are examined in conjunction with the signal-low
period of ports O0–O7 to see if any key is pressed. If
pressed, the corresponding key pressed register bit is
set. In the second key test period of 1.6ms, input level
at ports P0–P3 are examined again (debounce) to see if
the key is still pressed. If still pressed, the correspond-
ing debounce register bit is set. The debounce time
between key tests is 12.8ms.
16
Port Configuration Register
The port configuration register selects how the five port
pins are used. The port configuration register format is
described in Table 33.
Key Mask Registers
The Key_A Mask, Key_B Mask, Key_C Mask, and
Key_D Mask write-only registers (Table 34) configure
the key-scanning circuit to cause an interrupt only when
selected (masked) keys have been debounced. Each
bit in the register corresponds to one key switch. The bit
is clear to disable interrupt for the switch, and set to
enable interrupt. Keys are always scanned (if enabled
through the port configuration register), regardless of
the setting of these interrupt bits, and the key status is
stored in the appropriate Key_x pressed register.
Maxim Integrated
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