参数资料
型号: MAX6957ATL+T
厂商: Maxim Integrated
文件页数: 9/25页
文件大小: 0K
描述: IC DRVR DSPL LED 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: LED
配置: 7、16、20 段
接口: 4 线串行
电流 - 电源: 180µA
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port LED Display Driver and I/O Expander
MICROCONTROLLER
SERIAL DATA INPUT
SERIAL CS OUTPUT
SERIAL CLOCK OUTPUT
CS
SCLK
MAX6957
CS
SCLK
MAX6957
CS
SCLK
MAX6957
SERIAL DATA OUTPUT
DIN
DOUT
DIN
DOUT
DIN
DOUT
Figure 4. Daisy-Chain Arrangement for Controlling Multiple MAX6957s
CS
SCLK
DIN
D15
=0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
Figure 5. 16-Bit Write Transmission to the MAX6957
Control and Operation Using the
4-Wire Interface
Controlling the MAX6957 requires sending a 16-bit
word. The first byte, D15 through D8, is the command
address ( Table 3), and the second byte, D7 through
D0, is the data byte (Table 4).
Connecting Multiple MAX6957s to the 4-Wire Bus
Multiple MAX6957s may be daisy-chained by connect-
ing the DOUT of one device to the DIN of the next, and
driving SCLK and CS lines in parallel (Figure 4). Data at
DIN propagates through the internal shift registers and
appears at DOUT 15.5 clock cycles later, clocked out
on the falling edge of SCLK. When sending commands
to multiple MAX6957s, all devices are accessed at the
same time. An access requires (16 ? n) clock cycles,
where n is the number of MAX6957s connected togeth-
er. To update just one device in a daisy-chain, the user
can send the No-Op command (0x00) to the others.
D15 = 0
Writing Device Registers
The MAX6957 contains a 16-bit shift register into which
DIN data are clocked on the rising edge of SCLK, when
CS is low. When CS is high, transitions on SCLK have
no effect. When CS goes high, the 16 bits in the Shift
register are parallel loaded into a 16-bit latch. The 16
bits in the latch are then decoded and executed.
The MAX6957 is written to using the following
sequence:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN—D15 first, D0 last—
observing the setup and hold times (bit D15 is low,
indicating a write command).
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low).
5) Take SCLK low (if not already low).
Figure 5 shows a write operation when 16 bits are
transmitted.
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