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参数资料
| 型号： | MAX6964AEG+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 7/23页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 24-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 拓扑： | 开路漏极，PWM |
| 输出数： | 17 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，LED 闪烁器 |
| 类型 - 次要： | RGB，白色 LED |
| 频率： | 400kHz |
| 电源电压： | 2 V ~ 3.6 V |
| 输出电压： | 7V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
User RAM
The MAX6964 includes 2 register bytes, which are
available as general-user RAM (Table 2). These bytes
are reset to the value 0xFF on power-up and when the
RST input is taken low (Table 3).
Standby Mode
When the serial interface is idle and the PWM intensity
control is unused, the MAX6964 automatically enters
standby mode. If the PWM intensity control is used, the
operating current is slightly higher because the internal
PWM oscillator is running. When the serial interface is
active, the operating current also increases because
the MAX6964, like all I 2 C slaves, has to monitor every
transmission.
SDA
Serial Interface
Serial Addressing
The MAX6964 operates as a slave that sends and
receives data through an I 2 C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX6964 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX6964 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7k ? ,
is required on SDA. The MAX6964 SCL line operates
only as an input. A pullup resistor, typically 4.7k ? , is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
SCL
S
P
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX6964
START
CONDITION
Figure 3. Start and Stop Conditions
SDA
SCL
DATA LINE STABLE; CHANGE OF DATA
DATA VALID ALLOWED
Figure 4. Bit Transfer
START
CONDITION
CLOCK PULSE
FOR ACKNOWLEDGE
STOP
CONDITION
7-bit slave address plus R/ W bit, a register address
byte, 1 or more data bytes, and finally a STOP condi-
tion (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
SCL
1
2
8
9
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
SDA BY
TRANSMITTER
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
SDA BY
RECEIVER
S
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
Figure 5. Acknowledge
acknowledge clock pulse so the SDA line is stable low
SDA
A6
1
0
0
A2
0
0
R/W
ACK
MSB
SCL
Figure 6. Slave Address
LSB
_______________________________________________________________________________________
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