参数资料
型号: MAX6974ATL+T
厂商: Maxim Integrated
文件页数: 16/23页
文件大小: 0K
描述: IC LED DRIVER LINEAR 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
拓扑: PWM
输出数: 24
内部驱动器:
类型 - 主要: 通用
类型 - 次要: RGB
频率: 33MHz
电源电压: 3 V ~ 3.6 V
输出电压: 7V
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
工作温度: -40°C ~ 125°C
24-Output PWM LED Drivers
for Message Boards
The serial interface uses the continuously running
clock, CLKI, to synchronously transfer and latch data
(33MHz max). The MAX6974/MAX6975 sample inputs
DIN and LOADI on the rising edge of CLKI and update
outputs DOUT and LOADO on the rising edge of CLKI.
The MAX6974/MAX6975 specifications guarantee that
cascaded devices observe setup and hold timing from
device to device, making external buffers and clock
trees unnecessary, even in very large systems.
The high-speed CLKI, CLKO, DIN, and DOUT signals
use low-voltage differential signaling (LVDS), and the
less frequently changing control signals, LOADI and
LOADO, use standard CMOS. The differential signals
are generally referred to in unipolar shorthand; for
example, the statement “CLKI rising edge” means that
CLKI+ is rising, and CLKI- is falling.
The MAX6974/MAX6975 use LVDS drivers with differential
signaling (300mV nominal logic swing around a +1.2V
bias) and cascaded CMOS control signals to minimize
signal-path EMI and simplify interface timing and print-
ed-circuit board (PCB) layout. Note the differential
inputs for the first driver can be driven from +3.3V
CMOS using LVDS level translators, such as the
MAX9112 terminated with 110 Ω (see Figure 12).
A 25MHz to 33MHz clock frequency is recommended
to keep the display refresh rate high. When using the
MAX6975 in reduced global-intensity mode (GLB4 = 1
in configuration register), the recommended clock
frequency range is 6MHz to 33MHz.
Serial-Interface Protocol Structure
The MAX6974/MAX6975 serial interface transfers all
data and control functions using a protocol structure
consisting of header, data, and optional tail segments
transmitted in this sequence. The header and tail
CLKI+
CLKI-
t PD-CLKO
CLKO+
CLKO-
t SU-DIN
DIN+
t HD-DIN
DIN-
t PD-DOUT
DOUT+
DOUT-
t SU-LOADI
t HD-LOADI
LOADI
t PD-LOADO
LOADO
Figure 6. Serial-Interface Timing
16
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