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| 型号： | MAX7032EVSYS-315 |
| 厂商： | Maxim Integrated |
| 文件页数： | 5/32页 |
| 文件大小： | 0K |
| 描述： | EVAL KIT MAX7032 |
| 标准包装： | 1 |
| 系列： | * |
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Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 Ω system impedance, V AVDD = V DVDD = V PAVDD = V HVIN = +2.1V to +3.6V, f RF = 300MHz to 450MHz,
T A = -40°C to +125°C, unless otherwise noted. Typical values are at V PAVDD = V AVDD = V DVDD = V HVIN = +2.7V, T A = +25°C, unless
otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Gain
FSK DEMODULATOR
Conversion Gain
ANALOG BASEBAND
Maximum Data Filter Bandwidth
Maximum Data Slicer Bandwidth
Maximum Peak Detector
Bandwidth
15
2.0
50
100
50
mV/dB
mV/kHz
kHz
kHz
kHz
Maximum Data Rate
Manchester coded
NRZ
33
66
kbps
CRYSTAL OSCILLATOR
Crystal Frequency
Frequency Pulling by V DD
Crystal Load Capacitance
f XTAL
(Note 7)
(f RF - 10.7)/24
2
4.5
MHz
ppm/V
pF
SERIAL INTERFACE TIMING CHARACTERISTICS (see Figure 7)
Minimum SCLK Setup to Falling
Edge of CS
Minimum CS Falling Edge to
SCLK Rising-Edge Setup Time
Minimum CS Idle Time
Minimum CS Period
Maximum SCLK Falling Edge to
Data Valid Delay
Minimum Data Valid to SCLK
Rising-Edge Setup Time
Minimum Data Valid to SCLK
Rising-Edge Hold Time
Minimum SCLK High Pulse Width
Minimum SCLK Low Pulse Width
Minimum CS Rising Edge to
SCLK Rising-Edge Hold Time
Maximum CS Falling Edge to
Output Enable Time
Maximum CS Rising Edge to
Output Disable Time
t SC
t CSS
t CSI
t CS
t DO
t DS
t DH
t CH
t CL
t CSH
t DV
t TR
30
30
125
2.125
80
30
30
100
100
30
25
25
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
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| MAX7032EVSYS-433 | 功能描述:射频开发工具 MAX7032 Eval Kit RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
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