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参数资料
| 型号： | MAX7060ATG+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 24/31页 |
| 文件大小： | 0K |
| 描述： | IC TX ASK/FSK 280-450MHZ 24TQFN |
| 标准包装： | 2,500 |
| 频率： | 280MHz ~ 450MHz |
| 应用： | 通用 |
| 调制或协议： | ASK，OOK |
| 数据传输率 - 最大： | 140kbps |
| 功率 - 输出： | 15dBm |
| 电流 - 传输： | 34mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 电源电压： | 2.1 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | * |
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MAX7060
280MHz to 450MHz Programmable
ASK/FSK Transmitter
Table 14. FSK High-Frequency 1 (FHigh1) Register (Address: 0x0A)
BIT
7:0
NAME
fhi[7:0]
FUNCTION
8-bit lower byte of high-frequency divider for FSK
The 4 MSBs of FHigh0, fhi[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fhi[11:0])
are the fractional part of the divider.
Table 15. ASK Center-Frequency 0 (FCenter0) Register (Address: 0x0B)
BIT
7:0
NAME
fce[15:8]
8-bit upper byte of frequency divider for ASK
FUNCTION
Table 16. ASK Center-Frequency 1 (FCenter1) Register (Address: 0x0C)
BIT
7:0
NAME
fce[7:0]
8-bit lower byte of frequency divider for ASK
FUNCTION
The 4 MSBs of FCenter0, fce[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fce[11:0)
are the fractional part of the divider.
When fce[11:0] are all zeros and ASK mode is selected (mode bit = 0), the PLL works in the fixed-N mode, which
reduces current consumption and reference spurs. Set pllbw bit high (Conf0 register, bit 5). For all other combinations,
the PLL works in fractional-N mode.
Table 17. FSK Low-Frequency 0 (FLow0) Register (Address:0x0D)
BIT
7:0
NAME
flo[15:8]
FUNCTION
8-bit upper byte of low-frequency divider for FSK
Table 18. FSK Low-Frequency 1 (FLow1) Register (Address: 0x0E)
BIT
7:0
NAME
flo[7:0]
FUNCTION
8-bit lower byte of low-frequency divider for FSK
The 4 MSBs of FLow0, flo[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (flo[11:0])
are the fractional part of the divider.
Table 19. Maximum and Minimum Values fo r Frequency Divider
DECIMAL VALUE
12.0220
2.9536
fhi[15:0], fce[15:0], flo[15:0]
0xC05A
0x2F42
Table 20. Frequency-Load (FLoad) Register (Address: 0x0F)
24
BIT
0
NAME
hop
FUNCTION
Effectively changes the PLL frequency to the ones written in registers 0x09 to 0x0E. This is a self-reset bit
and is reset to zero after the operation is completed.
Maxim Integrated
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