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参数资料
| 型号： | MAX7060ATG+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 7/31页 |
| 文件大小： | 0K |
| 描述： | IC TX ASK/FSK 280-450MHZ 24TQFN |
| 标准包装： | 2,500 |
| 频率： | 280MHz ~ 450MHz |
| 应用： | 通用 |
| 调制或协议： | ASK，OOK |
| 数据传输率 - 最大： | 140kbps |
| 功率 - 输出： | 15dBm |
| 电流 - 传输： | 34mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 电源电压： | 2.1 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | * |
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MAX7060
280MHz to 450MHz Programmable
ASK/FSK Transmitter
AC ELECTRICAL CHARACTERISTICS (3V OPERATION) (continued)
( Typical Application Circuit , 50 I system impedance, tuned for 315MHz to 434MHz operation. V DD5 = V GPOVDD = V AVDD =
V DVDD = V PAVDD = 2.1V to 3.6V, f RF = 280MHz to 450MHz, f XTAL = 15MHz to 16MHz, T A = -40 N C to +125 N C, unless oth-
erwise noted. Typical values are at V DD5 = V GPOVDD = V AVDD = V DVDD = V PAVDD = 2.7V, T A = +25 N C, PA matched for
optimum output power, unless otherwise noted. All min and max values are 100% tested at T A = +125 N C and guaranteed by design
and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Carrier Harmonics
(Note 1)
Reference Spur
PAOUT Capacitor Tuning Range
-24
-43
0 to 7.75
dBc
dBc
pF
SERIAL PERIPHERAL INTERFACE (SPI) TIMING CHARACTERISTICS
(SPI timing characteristics are valid for both 3V and 5V modes. SPI timing is production tested at worst-case temperature and supply
with a clock frequency of 3MHz.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum SCLK_PWR0 Low to
Falling-Edge of CS _DEV Setup Time
Minimum CS _DEV Low to Rising
Edge of SCLK_PWR0 Setup Time
t SC
t CSS
30
15
ns
ns
Minimum SCLK_PWR0 Low to
Rising Edge of CS _DEV Setup
t HCS
60
ns
Time
Minimum SCLK_PWR0 Low After
Rising Edge of CS _DEV Hold Time
Minimum Data Valid to SCLK_
PWR0 Rising-Edge Setup Time
Minimum Data Valid to SCLK_
PWR0 Rising-Edge Hold Time
Minimum SCLK_PWR0 High Pulse
Width
Minimum SCLK_PWR0 Low Pulse
Width
Minimum CS _DEV High Pulse
Width
t HS
t DS
t DH
t CH
t CL
t CSH
15
30
15
120
120
120
ns
ns
ns
ns
ns
ns
Maximum Transition Time from
Falling-Edge of CS _DEV to Valid
GPO2_MOD
Maximum Transition Time from
Falling Edge of SCLK_PWR0 to
Valid GPO2_MOD
t CSG
t CG
C L = 10pF load capacitance from
GPO2_MOD to ground
C L = 10pF load capacitance from
GPO2_MOD to ground
400
400
ns
ns
Note 1: Supply current and output power are greatly dependent on board layout and PAOUT match.
Note 2: 50% duty cycle at 10kHz ASK data (Manchester coded).
Note 3: Dependent on PCB trace capacitance.
Maxim Integrated
7
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