MAX7060
280MHz to 450MHz Programmable
ASK/FSK Transmitter
pins. Connecting PAVOUT to PAOUT enables Tx power
control. In SPI mode, there are 31 power-control settings
in approximately 1dB monotonic steps. In manual mode,
four power-control settings are available.
ASK Envelope Shaping
The MAX7060 has two types of ASK envelope shaping:
digital shaping (SPI mode only) and analog shaping
through an internal resistor. Envelope shaping results
in a smaller spectral width of the modulated PA output
signal.
In digital shaping, the user can choose the final Tx power
setting, the power step size in units as small as 1dB, and
the step-time interval in units as small as 0.25 F s, when a
16MHz crystal is used. This shaping method causes the
PA to transmit an envelope that rises linearly in decibels
(exponentially in power) with time. Digital shaping is pro-
grammed through the SPI.
The analog shaping mode uses an internal envelope-
shaping resistor for ASK modulation, which connects
between PAVOUT and ROUT. When the ROUT pin
(rather than the PAVOUT pin) is connected to the PA
pullup inductor, the envelope-shaping resistor slows the
turn-on/turn-off time of the PA. The user can choose two
turn-on/turn-off times through the SPI. A single turn-on/
turn-off time is set internally in manual mode.
It should be noted that, by default, data pulses applied
to the DIN pin are internally lengthened by 64 crystal
clock cycles (4μs for a 16MHz crystal) to allow time
for the analog shaping to occur. For cases in which
no analog shaping is desired, the PA pullup inductor
must be connected to PAVOUT and the analog shaping
bits in the Conf0 register set to either anshp[1:0] = 00,
which leaves the extra 4μs pulse extension in place, or
to anshp[1:0] = 11, which removes the extra 4μs and
allows transmitted pulses to track the data present at the
DIN pin. If digital shaping is used, the PA pullup inductor
must be connected to PAVOUT and there is no 4μs pulse
extension, regardless of the status of the anshp[1:0] bits.
At low data rates, where shaping is not necessary and
the 4μs pulse lengthening has minimal impact on duty
cycle symmetry, it may be acceptable to use the default
configuration of anshp[1:0] = 00. For higher data rates, it
may be necessary to use anshp[1:0] = 11, to avoid duty
cycle skew. Another method to remove the pulse length-
ening is to apply a minimal amount of digital shaping,
by setting tstep[3:0] = 0001 and selecting pastep[4:0]
= papwr[4:0].
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Variable Capacitor
The MAX7060 has an internal set of capacitors that can
be switched in and out to present different capacitor
values at the PA output. The capacitors are connected
from the PA output to ground. This allows changing the
tuning network along with the synthesizer divide ratio
each time the transmitted frequency changes, making
it possible to maintain maximum transmitter power while
moving rapidly from one frequency to another.
In SPI mode, the variable capacitor is programmed
through a register setting. In manual mode, the capacitor
setting is programmed through the DIN pin.
The tuning capacitor has a nominal resolution of 0.25pF,
from 0 to 7.75pF.
Phase-Locked Loop (PLL)
The MAX7060 utilizes a fully integrated fractional-N
PLL for its frequency synthesizer. All PLL components,
including the loop filter, are included on-chip. Two loop
bandwidths can be selected in SPI mode. The synthe-
sizer has 16-bit fractional-N topology (4 bits integer, 12
bits fractional) with a divide ratio that can be set from 19
to 28, allowing the transmit frequency to be adjusted in
increments of f XTAL /4096.
The fractional-N architecture also allows exact FSK
frequency deviations to be programmed, completely
eliminating the problems associated with generating fre-
quency deviations by crystal oscillator pulling.
FSK deviations as low as Q 2kHz and as high as Q 100kHz
can be set in SPI mode. In manual mode, the user can
select between Q 16kHz and Q 50kHz.
The integer and fractional portions of the PLL divider
ratio set the transmit frequency. This is done by load-
ing the divide-ratio registers in SPI mode, or selecting
the states of the three frequency-control pins (FREQ2,
FREQ1, FREQ0) in manual mode. For ASK modulation,
the two 8-bit center-frequency registers (fce[15:0]) are
loaded with the divide ratio determined by the center
frequency and the crystal. For FSK modulation, the two
8-bit high (mark) frequency registers (fhi[15:0]) and the
two 8-bit low (space) frequency registers (flo[15:0]) are
loaded. The divide ratios for the fhi and flo are deter-
mined by the center frequency, the frequency deviation,
and the crystal frequency. Examples of typical settings
for ASK and FSK modulation are given in the SPI Mode
Settings section.
Maxim Integrated