参数资料
型号: MAX708TCUA-TG
厂商: ON Semiconductor
文件页数: 7/10页
文件大小: 0K
描述: IC MPU SUPERVISORY 3.08V 8MICRO
标准包装: 4,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 3.08V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: Micro8?
包装: 带卷 (TR)
其它名称: MAX708TCUA-TGOS
MAX707, MAX708
RESET Signal Integrity During Power?Down
The MAX707/708 RESET output is valid until V CC falls
below 1.0 V. Then, the output becomes an open circuit and
no longer sinks current. This means CMOS logic inputs of
components are required to follow the reset I/O of the m P, the
buffer should be connected as shown with the solid line.
BUFFERED
the m P will be floating at an undetermined voltage. Most
digital systems are completely shutdown well above this
voltage. However, in the case RESET must be maintained
valid to V CC = 0 V, a pull down resistor must be connected
from RESET to ground to discharge stray capacitances and
BUFFER
RESET TO
OTHER SYSTEM
COMPONENTS
hold the output low (Figure 14). This resistor value, though
VCC
VCC
not critical, should be chosen large enough not to load
RESET and small enough to pull it to ground. R = 100 k W
will be suitable for most applications.
MAX707/708
RESET
GND
4.7 k
m P
RESET
GND
VCC
MAX707/708
RESET
R
Figure 15. Interfacing to Bidirectional Reset I/O
Monitoring Additional Supply Levels
GND
100 k
When connecting a voltage divider to PFI and adjusting it
properly, you can monitor a voltage different than the
unregulated DC one. As shown in Figure 16, to increase
noise immunity, hysteresis may be added to the power?fail
Figure 14. Ensuring RESET Valid to V CC = 0 V
Interfacing with m Ps with Bidirectional I/O Pins
Some m Ps have bidirectional reset pins. If, for example,
the RESET output is driven high and the m P wants to put it
low, indeterminate logic level may result. This can be
avoided by adding a 4.7 k W resistor in series with the output
of the MAX707/708 (Figure 15). If there are other
components in the system that require a reset signal, they
should be buffered so as not to load the reset line. If the other
comparator just by a resistor between PFO and PFI. Not to
unbalance the potential divider network, R3 should be 10
times the sum of the two resistors R1 and R2. If required, a
capacitor between PFI and GND will reduce the sensitivity
of the circuit to high?frequency noise on the line being
monitored. The PFO output may be connected to MR input
to generate a low level on the RESET when V CC _1 drops out
of tolerance. Thus a RESET is generated when one of the
two voltages is below its threshold level.
V CC_1
R1
V CC_2
VCC
RESET
MAX707/708
V CC_3
VCC
RESET
m P
V CC_2
PFO
0V
1.25 ) 1.25 * Vcc_2
R2
PFI
MR
PFO
GND
GND
0V
VL + 1.25 ) R1
V L V H
V CC_1
R2 R3
R3
VH + 1.25
(1 ) R1
R2 ) R3 )
R2 R3
VHYS + VH * VL +
Figure 16. Monitoring Additional Supply Levels
http://onsemi.com
7
R1
Vcc_2
R3
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MAX708TESA 功能描述:监控电路 RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟(典型值):10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel
MAX708TESA+ 功能描述:监控电路 Single uPower Supervisor RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟(典型值):10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel