参数资料
型号: MAX7221CWG+T
厂商: Maxim Integrated
文件页数: 8/17页
文件大小: 0K
描述: IC DRVR DSPLY LED 8DIG 24SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
显示器类型: LED
配置: 7 段 + DP
接口: 4 线串行
数字或字符: 8 位数字
电流 - 电源: 330mA
电源电压: 4 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
MAX7219/MAX7221
Serially Interfaced, 8-Digit LED Display Drivers
Table 5. Code B Font
7-SEGMENT
REGISTER DATA
ON SEGMENTS = 1
CHARACTER
0
1
2
3
4
5
6
7
8
9
E
H
L
P
blank
D7*
D6–D4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DP*
A
1
0
1
1
0
1
1
1
1
1
0
1
0
0
1
0
B
1
1
1
1
1
0
0
1
1
1
0
0
1
0
1
0
C
1
1
0
1
1
1
1
1
1
1
0
0
1
0
0
0
D
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
0
E
1
0
1
0
0
0
1
0
1
0
0
1
1
1
1
0
F
1
0
0
0
1
1
1
0
1
1
0
1
1
1
1
0
G
0
0
1
1
1
1
1
0
1
1
1
1
1
0
1
0
*The decimal point is set by bit D7 = 1
Table 6. No-Decode Mode Data Bits and
Corresponding Segment Lines
A
Intensity Control
and Interdigit Blanking
The MAX7219/MAX7221 allow display brightness to be
controlled with an external resistor (R SET ) connected
between V+ and ISET. The peak current sourced from
the segment drivers is nominally 100 times the current
F
E
G
B
C
STANDARD 7-SEGMENT LED
entering ISET. This resistor can either be fixed or vari-
able to allow brightness adjustment from the front
panel. Its minimum value should be 9.53k Ω , which typi-
cally sets the segment current at 40mA. Display bright-
ness can also be controlled digitally by using the
intensity register.
D
DP
Digital control of display brightness is provided by an
internal pulse-width modulator, which is controlled by
D7
D6
REGISTER DATA
D5 D4 D3 D2
D1
D0
the lower nibble of the intensity register. The modulator
scales the average segment current in 16 steps from a
maximum of 31/32 down to 1/32 of the peak current set
Corresponding
Segment Line
DP
A
B
C
D
E
F
G
by R SET (15/16 to 1/16 on MAX7221). Table 7 lists the
intensity register format. The minimum interdigit blank-
ing time is set to 1/32 of a cycle.
8
Maxim Integrated
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