参数资料
型号: MAX724CCK
厂商: Maxim Integrated Products
文件页数: 6/13页
文件大小: 0K
描述: IC REG MULTI CONFIG ADJ TO220-5
标准包装: 50
类型: 降压(降压),升压(升压),反相,回扫
输出类型: 可调式
输出数: 1
输出电压: 2.5 V ~ 35 V
输入电压: 8 V ~ 40 V
PWM 型: 电流模式
频率 - 开关: 100kHz
电流 - 输出: 5A
同步整流器:
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: TO-220-5
包装: 管件
供应商设备封装: TO-220-5
5A/2A Step-Down, PWM,
Switch-Mode DC-DC Regulators
______________________________________________________________Pin Description
PIN
1
2
3
4
5
NAME
FB
V C
GND
V SW
V IN
FUNCTION
Feedback Input is the error amplifier's inverting input, and controls output voltage by adjusting switch duty cycle.
Input bias current is typically 0.5μA when the error amplifier is balanced (I OUT = 0V). FB also aids current limiting
by reducing the oscillator frequency when the output voltage is low. (See the Applications Information section.)
Error-Amplifier Output. A series RC network connected to this pin compensates the MAX724/MAX726. Output
swing is limited to about 5.8V in the positive direction and -0.7V in the negative direction. V C can also synchro-
nize the MAX724/MAX726 to an external clock. (See the Applications Information section).
Ground requires a short low-noise connection to ensure good load regulation. The internal reference is referred
to GND, so errors at this pin are multiplied by the error amplifier. See the Applications Information section for
grounding details.
Internal Power Switch Output. The S witch output can swing 35V below ground and is rated for 5A (MAX724), 2A
(MAX726).
V IN supplies power to the MAX724/MAX726's internal circuitry and also connects to the collector. V IN must be
bypassed with a low-ESR capacitor, typically 200μF or 220μF.
_________________Detailed Description
The MAX724/MAX726 are complete, single-chip, pulse-
width modulation (PWM), step-down DC-DC converters
(Figure 1). All oscillator (100kHz), control, and current-
limit circuitry, including a 5A power switch (2A for
MAX726), are included on-chip. The oscillator turns on
the switch (V SW ) at the beginning of each clock cycle.
The switch turns off at a point later in the clock cycle,
which is a function of the signal provided by the error
amplifier. The maximum switch duty cycle is approxi-
mately 93% at the MAX724/MAX726's 100kHz switch-
ing frequency.
Both the input (FB) and output (V C ) of the error
amplifier are brought out to simplify compensation.
Most applications require only a single series RC
network connected from V C to ground. The error
amplifier is a transconductance amplifier with a g M of
approximately 5000 μ mho. When slewing, V C can
source about 140 μ A, and sink about 1.1mA. This
asymmetry helps minimize start-up overshoot by
allowing the amplifier output to slew more quickly in
the negative direction.
Current limiting is provided by the current-limit com-
parator. If the current-limit threshold is exceeded, the
switch cycle terminates within about 600ns. The cur-
rent-limit threshold is internally set to approximately
6.5A (2.6A for MAX726). V SW is a power NPN, internally
driven by the PWM controller circuitry. V SW can swing
35V below ground and is rated for 5A (2A for MAX726).
Basic Step-Down Application
Figure 2 shows the MAX724/MAX726 in a basic step-
down DC-DC converter. Typical MAX724 waveforms
are shown in Figure 3 for V IN = 20V, V OUT = 5V, L =
50 μ H, and I OUT = 3A and 0.16A. Two sets of wave-
forms are shown. One set shows high load current (3A)
where inductor current never falls to zero during the
switch "off-cycle" (continuous-conduction mode, CCM).
The second set of waveforms, at low output current
(0.16A), shows inductor current at zero during the latter
half of the switch off-cycle (discontinuous-conduction
mode, DCM). The transition from CCM to DCM occurs
at an output current (I DCM ) that can be derived with the
following equation:
I DCM = (V OUT + V D ) [(V IN - V SW ) - (V OUT + V D )]
2 (V IN - V SW ) f OSC L
where V D is the diode forward voltage drop, V SW is the
voltage drop across the switch, and f OSC = 100kHz. In
most applications, the distinction between CCM and
DCM is academic since actual performance differences
are minimal. All CCM designs can be expected to exhibit
DCM behavior at some level of reduced load current.
_______________________________________________________________________________________
5
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