参数资料
型号: MAX7306AUB+
厂商: Maxim Integrated
文件页数: 4/23页
文件大小: 0K
描述: IC LED DRIVER LINEAR 10-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
拓扑: PWM
输出数: 4
内部驱动器:
类型 - 主要: 背光,LED 闪烁器
类型 - 次要: 白色 LED
频率: 1MHz
电源电压: 1.62 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)裸露焊盘
供应商设备封装: 10-µMAX-EP
包装: 管件
工作温度: -40°C ~ 125°C
SMBus/I 2 C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
PORT, INTERRUPT ( INT ), AND RESET ( RST ) TIMING CHARACTERISTICS
(V DD = 1.62V to 3.6V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V DD = 3.3V, V LA = 3.3V (MAX7307 only), T A =
+25°C.) (Note 1) (See Figures 14, 15, and 16)
PARAMETER
Oscillator Frequency
SYMBOL
f CLK
CONDITIONS
f CLK = internal oscillator
f CLK = external input
MIN
TYP
32
MAX
1
UNITS
kHz
MHz
Port Output Data Valid High Time
Port Output Data Valid Low Time (Internal or
External Oscillator Running)
Port Output Data Valid Low Time (Oscillator Not
Running)
Port Input Setup Time
Port Input Hold Time
INT Input Data Valid Time
INT Reset Delay Time from Acknowledge
RST Pulse Width
RST Rising to START Condition Setup Time
t PPVH
t PPVL1
t PPVL2
t PSU
t PH
t IV
t IR
t W
t RST
C L ≤ 100pF
C L ≤ 100pF (Note 2)
C L ≤ 100pF
C L = 100pF
C L = 100pF
C L = 100pF
C L = 100pF
0
4
500
900
40
4
1 / f CLK
4
4
μs
μs
μs
μs
μs
μs
μs
ns
ns
TIMING CHARACTERISTICS
(V DD = 1.62V to 3.6V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V DD = 3.3V, V LA = 3.3V (MAX7307 only), T A =
+25°C.) (Note 1) (See Figure 8)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency
Bus Timeout
Bus Free Time Between a STOP and a START Condition
Hold Time, (Repeated) START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
f SCL
t TIMEOUT
t BUF
t HD,STA
t SU,STA
t SU,STO
1.3
0.6
0.6
0.6
31
400
kHz
ms
μs
μs
μs
μs
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
t HD,DAT
t SU,DAT
t LOW
t HIGH
(Note 3)
100
1.3
0.7
0.9
μs
ns
μs
μs
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting
t R
t F
t F.TX
(Notes 2, 4)
(Notes 2, 4)
(Note 4)
20 + 0.1C b
20 + 0.1C b
20 + 0.1C b
300
300
250
ns
ns
ns
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
t SP
C b
(Note 5)
(Note 2)
50
400
ns
pF
Note 1: All parameters are tested at T A = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V IL of the SCL signal) to bridge the
undefined region of SCL’s falling edge.
Note 4: C b = total capacitance of one bus line in pF. t R and t F are measured between 0.3 x V DD and 0.7 x V DD .
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
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