参数资料
型号: MAX7320ATE+
厂商: Maxim Integrated Products
文件页数: 13/14页
文件大小: 0K
描述: IC I/O EXPANDER I2C 8B 16TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
接口: I²C
输入/输出数: 8
中断输出:
频率 - 时钟: 400kHz
电源电压: 1.71 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
供应商设备封装: 16-TQFN-EP(3x3)
包装: 管件
包括: POR
MAX7320
logic-high power-up state, and a logic-low selects a
logic-low power-up state for each set of four ports (see
Table 3). The output power-up logic level configuration
is correct for a standard I2C configuration, where SDA
or SCL appear to be connected to V+ by the external
I2C pullups.
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true; for example,
in true hot-swap applications in which there is legiti-
mate bus activity during power-up. Also, if SDA and
SCL are terminated with pullup resistors to a different
supply voltage than the MAX7320’s supply, and if that
pullup supply rises later than the MAX7320’s, then SDA
or SCL may appear at power-up to be connected to
GND. In such applications, use the four address combi-
nations that are selected by connecting address inputs
AD0 and AD2 to GND or V+ (shown in bold in Table 3).
These selections are guaranteed to be correct at
power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, be
aware that unexpected port power-up default states
may occur until the first I2C transmission (to any device,
not necessarily the MAX7320).
Port Outputs
Write one byte to the MAX7320 to set all output port
states simultaneously.
Serial Interface
Serial-Addressing
The MAX7320 operates as a slave that sends and
receives data through an I2C interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master initiates all data trans-
fers to and from the MAX7320, and generates the SCL
clock that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain output.
A pullup resistor, 4.7k
Ω (typ), is required on SDA. SCL
operates only as an input. A pullup resistor, 4.7k
Ω (typ),
is required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7320’s 7-bit slave
address plus R/W bit, one or more data bytes, and
finally a STOP condition (Figure 2).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
I2C Port Expander with Eight Push-Pull Outputs
8
_______________________________________________________________________________________
SCL
SDA
tR
tF
tVD,DAT
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT
tLOW
tHIGH
tHD,STA
Figure 1. 2-Wire Serial-Interface Timing Details
SDA
SCL
START
CONDITION
STOP
CONDITION
SP
Figure 2. START and STOP Conditions
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