参数资料
型号: MAX7360ETL+T
厂商: Maxim Integrated Products
文件页数: 2/32页
文件大小: 0K
描述: IC CTRLR KEY-SW I2C 40TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 控制器
输入类型: 逻辑
输出类型: 逻辑
接口: I²C,2 线串口
电流 - 电源: 50µA
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
10
Maxim Integrated
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
MAX7360
Key-Scan Controller
Key inputs are scanned statically, not dynamically,
to ensure low-EMI operation. As inputs only toggle in
response to switch changes, the key matrix can be
routed closer to sensitive circuit nodes.
The key-scan controller debounces and maintains a FIFO
of keypress and release events (including autorepeated
keypresses, if autorepeat is enabled). Table 2 shows the
key-switch order. The user-programmable key-switch
debounce time, and autosleep timer, is derived from the
64kHz clock, which in turn is derived from the 128kHz
oscillator. Time delay for autorepeat and key-switch
interrupt is based on the key-switch debounce time.
Keys FIFO Register (0x00)
The keys FIFO register contains the information pertaining
to the status of the keys FIFO, as well as the key events
that have been debounced (see Table 7 in the Register
Tables section). Bits D0–D5 denote which of the 64 keys
have been debounced and the keys are numbered as in
Table 2.
D7 indicates if there is more data in the FIFO, except
when D5:D0 indicate key 63 or key 62. When D5:D0
indicate key 63 or key 62, the host should read one more
time to determine whether there is more data in the FIFO.
Use key 62 and key 63 for rarely used keys. D6 indicates
if it is a keypress or release event, except when D5:D0
indicate key 63 or key 62.
Reading the key-scan FIFO clears the interrupt INTK
depending on the setting of bit D5 in the configuration
register (0x01).
Configuration Register (0x01)
The configuration register controls the I2C bus timeout
feature, enables key-release detection, enables autowake,
and determines how INTK is deasserted. Write to bit D7
to put the MAX7360 into sleep mode or operating mode.
Autosleep and autowake, when enabled, also change the
status of D7 (see Table 8 in the Register Tables section).
Debounce Register (0x02)
The debounce register sets the time for each debounce
cycle, as well as setting whether the GPO ports are
enabled or disabled. Bits D0–D4 set the debounce time
in increments of 1ms starting at 9ms and ending at 40ms
(see Table 9 in the Register Tables section). Bits D5, D6,
and D7 set which of the GPO ports is enabled. Note the
GPO ports are enabled only in the combinations shown
in Table 9, from all disabled to all enabled.
Key-Switch Interrupt Register (0x03)
The interrupt register contains information related to the
settings of the interrupt request function, as well as the
status of the INTK output, which can also be configured
as a GPO. If bits D0–D7 are set to 0x00, the INTK output
is configured as a GPO that is controlled by bit D1 in the
port register. There are two types of interrupts, the FIFO-
based interrupt and time-based interrupt. Set bits D0–D4
to assert interrupts at the end of the selected number of
debounce cycles following a key event (see Table 10 in
the Register Tables section). This number ranges from
1–31 debounce cycles. Setting bits D7, D6, and D5 set
the FIFO-based interrupt when there are 2–14 key events
stored in the FIFO. Both interrupts can be configured
simultaneously and INTK asserts depending on which
condition is met first. INTK deasserts depending on the
status of bit D5 in the configuration register.
Ports Register (0x04)
The ports register sets the values of PORT2–PORT7 and
the INTK port, when configured, as open-drain GPOs.
Table 2. Key-Switch Mapping
*These columns can be configured as GPOs.
PIN
COL0
COL1
COL2*
COL3*
COL4*
COL5*
COL6*
COL7*
ROW0
KEY 0
KEY 8
KEY 16
KEY 24
KEY 32
KEY 40
KEY 48
KEY 56
ROW1
KEY 1
KEY 9
KEY 17
KEY 25
KEY 33
KEY 41
KEY 49
KEY 57
ROW2
KEY 2
KEY 10
KEY 18
KEY 26
KEY 34
KEY 42
KEY 50
KEY 58
ROW3
KEY 3
KEY 11
KEY 19
KEY 27
KEY 35
KEY 43
KEY 51
KEY 59
ROW4
KEY 4
KEY 12
KEY 20
KEY 28
KEY 36
KEY 44
KEY 52
KEY 60
ROW5
KEY 5
KEY 13
KEY 21
KEY 29
KEY 37
KEY 45
KEY 53
KEY 61
ROW6
KEY 6
KEY 14
KEY 22
KEY 30
KEY 38
KEY 46
KEY 54
KEY 62
ROW7
KEY 7
KEY 15
KEY 23
KEY 31
KEY 39
KEY 47
KEY 55
KEY 63
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