参数资料
型号: MAX768EEE+T
厂商: Maxim Integrated Products
文件页数: 6/12页
文件大小: 0K
描述: IC REG SWTCHD CAP DBL INV 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 切换式电容器(充电泵),倍增器,反相
输出类型: 固定
输出数: 2
输出电压: ±11V
输入电压: 2.5 V ~ 5.5 V
频率 - 开关: 25kHz,100kHz
电流 - 输出: 5mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 16-QSOP
Low-Noise, Dual-Output, Regulated Charge Pump
for GaAsFET, LCD, and VCO Supplies
______________________________________________________________Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
C1-
GND
C2-
V-
NOUT
SETN
NSHDN
PSHDN
SYNC
RDY
SETP
POUT
V+
C1+
IN
C2+
FUNCTION
Negative Terminal of the Doubler Charge-Pump Capacitor. See Table 2 for capacitor selection.
Ground
Negative Terminal of the Inverter Charge-Pump Capacitor
Inverter Charge-Pump Output. See Table 2 for capacitor selection.
Negative Regulator Output. See Table 2 for capacitor selection.
Set Negative Output Voltage Input. Connect SETN to GND for factory-preset -5V. Connect a resistor
divider between NOUT, SETN, and GND for custom output voltage setting.
Negative-Supply Shutdown Input. Pull NSHDN low to turn off the inverting charge pump, the negative reg-
ulator, and the bias-ready indicator. If PSHDN is also low, the part completely shuts down.
Positive-Supply Shutdown Input. Pull PSHDN low to turn off the positive regulator. If NSHDN is also low,
the part completely shuts down.
Clock Synchronizing Input. Connect an external 20kHz ≤ f CLK ≤ 240kHz to SYNC to synchronize the
MAX768 to that frequency. Connect SYNC to GND to select the internal 25kHz clock, or to IN for the inter-
nal 100kHz clock.
Output-Ready Indicator. This open-drain output pulls to GND when the negative output voltage (NOUT) is
within 10% of the regulation voltage.
Set Positive Output Voltage Input. Connect SETP to GND for factory-preset +5V output. Connect a resistor
divider between POUT, SETP, and GND for custom output voltage setting.
Positive Regulator Output. See Table 2 for capacitor selection.
Doubler Charge-Pump Output. See Table 2 for capacitor selection.
Positive Terminal of the Doubler Charge-Pump Capacitor. See Table 2 for capacitor selection.
Supply (3V to 5.5V). Bypass IN with 4.7μF to GND.
Positive Terminal of the Inverter Charge-Pump Capacitor. See Table 2 for capacitor selection.
6
_______________________________________________________________________________________
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