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参数资料
| 型号： | MAX768EEE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | IC REG SWTCHD CAP DBL INV 16QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 切换式电容器（充电泵），倍增器，反相 |
| 输出类型： | 固定 |
| 输出数： | 2 |
| 输出电压： | ±11V |
| 输入电压： | 2.5 V ~ 5.5 V |
| 频率 - 开关： | 25kHz，100kHz |
| 电流 - 输出： | 5mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-QSOP |
Low-Noise, Dual-Output, Regulated Charge Pump
for GaAsFET, LCD, and VCO Supplies
IN
V+
C1+
VOLTAGE
P
MAX768
POUT
C1-
DOUBLER
SETP
CONNECT TO GND
PSHDN
SYNC
NSHDN
C2+
SHDN
+1.25V
REF
-1.25V
N
TO SET V POUT = +5V
GND
RDY
Figure 1. Functional Diagram
C2-
V-
VOLTAGE
INVERTER
N
SETN
CONNECT TO GND
TO SET V NOUT = -5V
NOUT
_______________Detailed Description
The MAX768 requires only seven external capacitors to
implement a regulated voltage doubler/inverter. These
can be ceramic or polarized electrolytic capacitors rang-
ing from 2.2μF to 47μF. Figure 1 is a functional diagram of
the MAX768. The applied input voltage (V IN ) is first dou-
bled to a value of 2V IN by a capacitor charge pump and
then stored in the V+ reservoir capacitor. Next, the volt-
age at V+ is inverted to -2V IN and stored at the V- reser-
voir capacitor. The voltages at V+ and V- are then linear
regulated and appear at POUT and NOUT, respectively.
The ripple noise induced by the doubling and inverting
__________Applications Information
Setting the Output Voltage
Connect SETP or SETN directly to GND to select a fixed
+5V or -5V output voltage, respectively (Figure 2).
Select an alternative voltage for either output by con-
necting SETP or SETN to the midpoint of a resistor volt-
age divider from POUT or NOUT, respectively, to GND
(Figure 3). (2 x V IN ) must be 1.0V above the absolute
value of the output voltage to ensure proper regulation.
Calculate the output voltage from the formulas below.
Choose R1 and R3 at between 100k ? to 400k ? .
( )
? V PSET REF
? 1 ?
( )
? V NSET REF
? 1 ?
charge pump is reduced by the linear regulators to
1.2mVp-p for POUT and 1.7mVp-p for NOUT. In addition,
the linear regulator’s excellent AC rejection attenuates
noise from the incoming supply. A minimum of 5mA is
available at each output. When NOUT is more negative
than 90% of the regulated output voltage, the open-drain
RDY output pulls to GND.
The charge pump operates in three modes: when SYNC
? V POUT
R2 = R1 ?
? V NOUT
R4 = R3 ?
?
?
?
?
= GND, the charge pump operates at 25kHz; when
SYNC = IN, it operates at 100kHz, or SYNC can be over-
driven with an external clock in the 20kHz to 240kHz
range. The clock must have a 40% to 60% duty cycle.
where V PSET REF = 1.25V (typical) and
V NSET REF = -1.25V (typical).
_______________________________________________________________________________________
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