参数资料
型号: MAX795SCSA+T
厂商: Maxim Integrated Products
文件页数: 11/20页
文件大小: 0K
描述: IC SUPERVISOR MPU 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.925V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
V CC
V RST
V CC
MAX793/MAX794
4.7k ?
WDO
RESET
TO μ P
RESET
WDO
t RP
V CC
MR
WDI
t WD
WDO
~ 10 μ s
WDO CONNECTED TO μ P INTERRUPT
RESET
WDI
t RP
t WP
t RP
RESET PULLED UP TO V CC
Figure 5. Watchdog Timing Relationship
a reset occurs or when a transition (low-to-high or high-
to-low) takes place at WDI. As long as reset is assert-
ed, the timer remains cleared and does not count. As
soon as reset is released or WDI changes state, the
timer starts counting (Figure 5). WDI can detect pulses
as short as 100ns. Unlike the 5V MAX690 family, the
watchdog function cannot be disabled.
Watchdog Output (MAX793/MAX794)
In the MAX793/MAX794, WDO remains high ( WDO is
pulled up to V CC ) if there is a transition or pulse at WDI
during the watchdog timeout period. WDO goes low if
no transition occurs at WDI during the watchdog timeout
period. The watchdog function is disabled and WDO is
a logic high when reset is asserted if V CC is above V SW .
WDO is a logic low when V CC is below V SW .
If a system reset is desired on every watchdog fault,
simply diode-OR connect WDO to MR (Figure 6).
When a watchdog fault occurs in this mode, WDO goes
low, pulling MR low, which causes a reset pulse to be
issued. Ten microseconds after reset is asserted, the
watchdog timer clears and WDO returns high. This
delay results in a 10μs pulse at WDO , allowing external
circuitry to capture a watchdog fault indication. A con-
tinuous high or low on WDI causes 200ms reset pulses
to be issued every 1.6s.
Figure 6. Generating a Reset on Each Watchdog Fault
Chip-Enable Signal Gating
Internal gating of chip-enable (CE) signals prevents erro-
neous data from corrupting CMOS RAM in the event of an
undervoltage condition. The MAX793/MAX794/MAX795
use a series transmission gate from CE IN to CE OUT
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transi-
tions. When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay from CE IN
to CE OUT enables these μP supervisors to be used with
most μPs. If CE IN is low when reset asserts, CE OUT
remains low for typically 10μs to permit completion of the
current write cycle.
Chip-Enable Input
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when V CC passes the
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
age at CE IN is high. If CE IN is low when reset asserts,
the CE transmission gate disables at the moment CE IN
goes high, or 10μs after reset asserts, whichever
occurs first (Figure 8). This permits the current write
cycle to complete during power-down.
______________________________________________________________________________________
11
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