参数资料
型号: MAX795SCSA+T
厂商: Maxim Integrated Products
文件页数: 4/20页
文件大小: 0K
描述: IC SUPERVISOR MPU 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.925V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 3.17V to 5.5V for the MAX793T/MAX795T, V CC = 3.02V to 5.5V for the MAX793S/MAX795S, V CC = 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, V BATT = 3.6V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)
PARAMETER
RESET Output-Voltage Low
BATT ON Output-
Voltage Low
All Inputs Including PFO
(Note 10)
SYMBOL
V OL
V OL
V IH
V IL
CONDITIONS
MAX79_C, V BATT = V CC = 1.0V, I SINK = 40μA
MAX79_E, V BATT = V CC = 1.2V, I SINK = 200μA
I SINK = 3.2mA, V CC = V RST max
V RST max < V CC < 5.5V
MIN
0.3V CC
TYP
0.13
0.17
MAX
0.3
0.3
0.2V CC
0.7V CC
UNITS
V
V
V
MANUAL RESET INPUT
MR Pulse Width
t MR
MAX793/MAX794 only
100
ns
MR -to-Reset Delay
t MD
MAX793/MAX794 only
75
250
ns
MR Pullup Current
MAX793/MAX794 only, MR = 0V
25
70
250
μA
CHIP-ENABLE GATING
CE IN Leakage Current
CE IN-to- CE OUT
Resistance
I LEAK
Disable mode
Enable mode, V CC = V RST max
±10
46
nA
?
CE IN-to- CE OUT
Propagation Delay
V CC = V RST max, Figure 9
2
7
ns
CE OUT Drive from CE IN
V OH
V OL
V CC = V RST max, I OUT = -1mA,
V CE IN = V CC
V CC = V RST max, I OUT = 1.6mA,
V CE IN = 0V
0.8V CC
0.2V CC
V
Reset to CE OUT High Delay
10
μs
CE OUT Output-Voltage
High (reset active)
V OH
I OH = 500μA, V CC < 2.3V
0.8V BATT
V
WATCHDOG (MAX793/MAX794 only)
WDI Input Current
Watchdog Timeout Period
t WD
0V < V CC < 5.5V
-1
1.00
0.01
1.60
1
2.25
μA
s
WDI Pulse Width
100
ns
Note 1: V CC supply current, logic-input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),
PFI functionality (MAX793/MAX794), and state of RESET and RESET (MAX793/MAX794) tested at V BATT = 3.6V and V CC =
5.5V. The state of RESET is tested at V CC = V CC min.
Note 2: Tested at V BATT = 3.6V, V CC = 3.5V and 0V. The battery current rises to 10μA over a narrow transition window around V CC
= 1.9V.
Note 3: Leakage current into the battery is tested under the worst-case conditions at V CC = 5.5V, V BATT = 1.8V and V CC = 1.5V,
V BATT = 1.0V.
Note 4: Guaranteed by design.
Note 5: When V SW > V CC > V BATT , OUT remains connected to V CC until V CC drops below V BATT . The V CC -to-V BATT comparator
has a small 15mV typical hysteresis to prevent oscillation. For V CC < 1.75V (typical), OUT switches to BATT regardless of
V BATT .
Note 6: When V BATT > V CC > V SW , OUT remains connected to V CC until V CC drops below the battery switch threshold (V SW ).
Note 7: OUT switches from BATT to V CC when V CC rises above the reset threshold, if V BATT > V RST . In this case, switchover back
to V CC occurs at the exact voltage that causes reset to be asserted, however, switchover occurs 200ms prior to reset. If
V BATT < V RST , OUT switches from BATT to V CC when V CC exceeds V BATT .
Note 8: The reset threshold tolerance is wider for V CC rising than for V CC falling to accommodate the 10mV typical hysteresis,
which prevents internal oscillation.
Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).
Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.
4
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