参数资料
型号: MAX795TESA+T
厂商: Maxim Integrated Products
文件页数: 8/20页
文件大小: 0K
描述: IC SUPERVISOR MPU 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 3.075V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_______________Detailed Description
General Timing Characteristics
The MAX793/MAX794/MAX795 are designed for 3.3V
and 3V systems, and provide a number of supervisory
functions (see the Selector Guide on the front page).
Figures 1 and 2 show the typical timing relationships of
the various outputs during power-up and power-down
with typical V CC rise and fall times.
Manual Reset Input (MAX793/MAX794)
Many microprocessor-based products require manual-
reset capability, allowing the operator, a test technician,
or external logic circuitry to initiate a reset. On the
MAX793/MAX794, a logic low on MR asserts reset. Reset
remains asserted while MR is low, and for t RP (200ms)
after it returns high. During the first half of the reset time-
V RST
V LL
out period (t RP ), the state of MR is ignored if PFO is exter-
nally forced low to facilitate enabling the battery fresh-
ness seal. MR has an internal 70μA pullup current, so it
can be left open if it is not used. This input can be driven
with TTL- or CMOS-logic levels, or with open-drain/collec-
tor outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function; exter-
nal debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environ-
ment, connect a 0.1μF capacitor from MR to ground to
provide additional noise immunity.
Reset Outputs
A microprocessor’s (μP’s) reset input starts the μP in a
known state. These MAX793/MAX794/MAX795 μP
supervisory circuits assert a reset to prevent code exe-
cution errors during power-up, power-down, and
V SW
V CC
5 μ s
V LOWLINE (MAX793/MAX794)
t RP
V RESET (PULLED UP TO V CC )
V RESET (MAX793/MAX794)
t RP
V CE OUT
V WDO
(MAX793/MAX794)
V BOK
(MAX793)
PFO
(MAX793/MAX794)
BATT ON
V BATT
25 μ s
25 μ s
25 μ s
25 μ s
t RP / 2
t RP / 2
(PFO FOLLOWS PFI)
SHOWN FOR V CC = 0V to 3.3V, V BATT = 3.6V, CE IN = GND.
TYPICAL PROPAGATION DELAYS REFLECT A 40mV OVERDRIVE.
MAX794: V RESET IN = V CC (V RST IN / V RST )
Figure 1. Timing Diagram, V CC Rising
8
_______________________________________________________________________________________
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