参数资料
型号: MAX8521EWX+T
厂商: Maxim Integrated Products
文件页数: 16/18页
文件大小: 0K
描述: IC DRVR PWR TEC 36-WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 热电冷却器
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-UFBGA,WLCSP
供应商设备封装: 36-WLP(3.07x3.07)
包装: 带卷 (TR)
Smallest TEC Power Drivers for Optical
Modules
6) To ensure high DC-loop gain and minimum loop
error, keep the board layout adjacent to the negative
input pin of the integrator (U2 in Figure1) clean and free
of moisture. Any contamination or leakage current into
this node can act to lower the DC gain of the integrator
Refer to the MAX8520/MAX8521 evaluation kit for a
PCB layout example.
Chip Information
PROCESS: BiCMOS
which can degrade the accuracy of the thermal loop. If
space is available, it can also be helpful to surround the
negative input node of the integrator with a grounded
guard ring.
Pin Configurations
TOP VIEW
TOP VIEW
BUMPS ON BOTTOM
+
F6
F5
F4
F3
F2 F1
LX1
1
15
LX2
PVDD2 PVDD2
CS
OS1
PVDD1 PVDD1
E6
E5
E2
E1
PGND1
2
14
PGND2
LX2
LX2
LX1
LX1
SHDN
COMP
3
4
MAX8520/
MAX8521
13
12
FREQ
V DD
D6 D5 D4 D3 D2 D1
PGND2 PGND2 PGND2 PGND1 PGND1 PGND1
ITEC
5
EP
11
GND
C6
OS2
C5
FREQ
C4
GND2
C3
GND2
C2 C1
COMP SHDN
B6
VDD
B5
GND2
B2
GND2
B1
ITEC
A6
A5
A4
A3
A2 A1
TQFN
GND
CTLI
REF
MAXV
MAXIP MAXIN +
CONNECT EP TO GND
MAX8521
UCSP/WLP
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE
20 TQFN-EP
6 x 6 UCSP
36 WLP
PACKAGE CODE
T2055+4
B36-2
W363A3+2
OUTLINE NO.
LAND
PATTERN NO.
16
______________________________________________________________________________________
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